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1. 发明授权

US07783911B2 Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements 有权
标题翻译：可编程总线驱动器启动延迟/周期延迟以减少弹性接口弹性要求
公开(公告)号：US07783911B2
公开(公告)日：2010-08-24
申请号：US11426666
申请日：2006-06-27
申请人： Jonathan Y. Chen , Patrick J. Meaney , Gary A. Van Huben , David A. Webber
发明人： Jonathan Y. Chen , Patrick J. Meaney , Gary A. Van Huben , David A. Webber
IPC分类号： G06F11/00 , G06F13/42 , H04L7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1069
摘要： A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.
摘要翻译：双数据速率弹性界面，其中可编程锁定级提供弹性延迟，优选地在弹性界面的驱动侧。然而，本发明不限于驱动器侧/芯片，也可以在接收机侧/芯片中实现。然而，由于弹性接口的接收机侧已经具有复杂的逻辑，因此本发明通常在驱动侧实现。接口驱动芯片侧的可编程锁存级通常可以以本地时钟频率（与弹性接口总线时钟频率相同的频率）工作，而这又是接收锁存级的双倍数据速率的一半操作，从而减少接口接收机中的逻辑和存储资源。在本地时钟频率是弹性接口总线时钟频率的两倍的情况下，也可以使用可编程锁存级。

2. 发明申请

US20070300099A1 Programmable Bus Driver Launch Delay/Cycle Delay to Reduce Elastic Interface Elasticity Requirements 有权
标题翻译：可编程总线驱动器启动延迟/周期延迟以减少弹性接口弹性要求
公开(公告)号：US20070300099A1
公开(公告)日：2007-12-27
申请号：US11426666
申请日：2006-06-27
申请人： Jonathan Y. Chen , Patrick J. Meaney , Gary A. Van Huben , David A. Webber
发明人： Jonathan Y. Chen , Patrick J. Meaney , Gary A. Van Huben , David A. Webber
IPC分类号： G06F1/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1069
摘要： A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.
摘要翻译：双数据速率弹性界面，其中可编程锁定级提供弹性延迟，优选地在弹性界面的驱动侧。然而，本发明不限于驱动器侧/芯片，也可以在接收机侧/芯片中实现。然而，由于弹性接口的接收机侧已经具有复杂的逻辑，因此本发明通常在驱动侧实现。接口驱动芯片侧的可编程锁存级通常可以以本地时钟频率（与弹性接口总线时钟频率相同的频率）工作，而这又是接收锁存级的双倍数据速率的一半操作，从而减少接口接收机中的逻辑和存储资源。在本地时钟频率是弹性接口总线时钟频率的两倍的情况下，也可以使用可编程锁存级。

3. 发明申请

US20070300096A1 Late Data Launch for a Double Data Rate Elastic Interface 失效
标题翻译：延迟数据启动双数据速率弹性接口
公开(公告)号：US20070300096A1
公开(公告)日：2007-12-27
申请号：US11426671
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译：双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。

4. 发明申请

US20070300032A1 Early Directory Access of A Double Data Rate Elastic Interface 失效
标题翻译：双数据速率弹性接口的早期目录访问
公开(公告)号：US20070300032A1
公开(公告)日：2007-12-27
申请号：US11426675
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译：一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。有很多应用程序。在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。

5. 发明申请

US20070300095A1 Double Data Rate Chaining for Synchronous DDR Interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US20070300095A1
公开(公告)日：2007-12-27
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

6. 发明授权

US07739538B2 Double data rate chaining for synchronous DDR interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US07739538B2
公开(公告)日：2010-06-15
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F5/06 , G11C8/16
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

7. 发明授权

US06954870B2 Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface 失效
标题翻译：用于源同步波流水线接口的接收机延迟检测和延迟最小化的方法
公开(公告)号：US06954870B2
公开(公告)日：2005-10-11
申请号：US10096382
申请日：2002-03-12
申请人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
发明人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
IPC分类号： G06F1/12 , G06F3/00 , H04L7/00 , H04L7/10
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/005
摘要： A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.
摘要翻译：提供校准弹性界面的方法以通过界面自动实现最小的循环延迟。现有的自对准接口（即弹性接口）用于在一个周期内去偏移，并且在给定的编程的目标周期上对数据进行分段以使其达到。但是，这个目标周期必须提前计算，并且可能会大于需要的时间，从而在接口上造成更多的延迟。该方法用于确定最早的目标周期（带或不带附加保护带）。该目标周期用于自动调整接口以实现最早的目标周期。最早的目标周期的确定可以进行一次，连续或使用样本窗口。该方法还可用于在其边界具有频率乘法器或相移的接口。

8. 发明授权

US07882322B2 Early directory access of a double data rate elastic interface 失效
标题翻译：早期目录访问的双倍数据速率弹性界面
公开(公告)号：US07882322B2
公开(公告)日：2011-02-01
申请号：US11426675
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译：一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。有很多应用程序。在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。

9. 发明授权

US07752475B2 Late data launch for a double data rate elastic interface 失效
标题翻译：推迟数据速率的双倍数据速率弹性界面
公开(公告)号：US07752475B2
公开(公告)日：2010-07-06
申请号：US11426671
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译：双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。

10. 发明授权

US06934867B2 Digital system having a multiplicity of self-calibrating interfaces 失效
标题翻译：具有多个自校准接口的数字系统
公开(公告)号：US06934867B2
公开(公告)日：2005-08-23
申请号：US10150231
申请日：2002-05-17
申请人： Jonathan Y. Chen , Patrick J. Meaney , William J. Scarpero, Jr.
发明人： Jonathan Y. Chen , Patrick J. Meaney , William J. Scarpero, Jr.
IPC分类号： G06F13/42 , H04L7/00 , H04L7/04 , H04L7/08 , G06F1/04
CPC分类号： H04L7/04 , H04L7/005
摘要： A method of calibrating an interface is provided to automatically achieve a minimal cycle latency while maintaining synchronous data arrival between a multiplicity of self-aligning interfaces. Independent self-alignment interfaces may de-skew data bits and have them arrive on a minimum cycle boundary. However, if all the interfaces do not arrive on the same cycle, SMP designs may not function properly. For instance, with a single control chip and multiple data chips on an AMP node, the control chip often sends out controls to the dataflow chips. If the data arriving on the elastic interfaces is not synchronized with the controls, the data is not routed properly. The method employs a calibration pattern to determine the latest cycle that data is received across the elastic interfaces and calculates the target cycle for all the interfaces to match this latest cycle. The target cycle is fed back into the design and the data is received synchronously, also provided is a test to ensure that the data arrives synchronously.
摘要翻译：提供校准接口的方法，以便在多个自对准接口之间保持同步数据到达时自动实现最小的周期延迟。独立的自对准接口可以对数据位进行偏移，并使它们到达最小周期边界。但是，如果所有接口都没有在同一周期内到达，则SMP设计可能无法正常工作。例如，在AMP节点上使用单个控制芯片和多个数据芯片，控制芯片通常会向数据流芯片发出控制。如果到达弹性接口的数据与控件不同步，则数据路由不正确。该方法采用校准模式来确定在弹性接口上接收数据的最新周期，并计算所有接口的目标周期以匹配该最新周期。目标周期被反馈到设计中并且同步地接收数据，还提供了确保数据同步到达的测试。

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