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1. 发明授权

US08039347B2 Semiconductor device having vertically aligned pillar structures that have flat side surfaces and method for manufacturing the same 有权
标题翻译：具有垂直排列的具有平坦侧表面的柱结构的半导体器件及其制造方法
公开(公告)号：US08039347B2
公开(公告)日：2011-10-18
申请号：US12491565
申请日：2009-06-25
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim , Young Ju Lee
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim , Young Ju Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L29/66666
摘要： A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures.
摘要翻译：提出了具有由具有平坦侧表面的柱结构制成的垂直排列的晶体管的半导体器件。半导体器件包括半导体衬底，间隔物和栅极。半导体衬底具有平坦的侧表面的柱结构。间隔物仅在支柱结构的上部的侧壁上。门围绕柱结构的下部。

2. 发明授权

US07871913B2 Method for manufacturing semiconductor device having vertical transistor 有权
标题翻译：具有垂直晶体管的半导体器件的制造方法
公开(公告)号：US07871913B2
公开(公告)日：2011-01-18
申请号：US12335668
申请日：2008-12-16
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66666 , H01L29/4236 , H01L29/42376 , H01L29/7827
摘要： A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
摘要翻译：一种制造具有垂直晶体管的半导体器件的方法包括：在半导体衬底上形成硬掩模以暴露半导体衬底的部分。然后蚀刻半导体衬底的暴露部分以在半导体衬底中限定凹槽。在硬掩模和凹槽的表面上形成栅极导电层至不完全填充凹槽的厚度。牺牲层形成在栅极导电层上以完全填充凹槽。去除牺牲层的部分厚度以露出栅极导电层，并且去除形成在硬掩模上的栅极导电层的部分以及沟槽上部的侧壁上的部分。剩余的牺牲层被完全去除。通过蚀刻栅极导电层在栅极的下部的侧壁上形成栅极。

3. 发明授权

US08384135B2 Phase-change random access memory device and method of manufacturing the same 有权
标题翻译：相变随机存取存储器件及其制造方法
公开(公告)号：US08384135B2
公开(公告)日：2013-02-26
申请号：US13164490
申请日：2011-06-20
申请人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
发明人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：相变随机存取存储器件包括半导体衬底，形成在半导体衬底上的底部电极结构，包括与底部电极接触的导电材料层的圆柱形底部电极接触和圆柱形相变与底部电极接触的材料层。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

4. 发明申请

US20110240950A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：相变随机访问存储器件及其制造方法
公开(公告)号：US20110240950A1
公开(公告)日：2011-10-06
申请号：US13164490
申请日：2011-06-20
申请人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
发明人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：相变随机存取存储器件包括半导体衬底，形成在半导体衬底上的底部电极结构，包括与底部电极接触的导电材料层的圆柱形底部电极接触和圆柱形相变与底部电极接触的材料层。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

5. 发明授权

US07045450B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07045450B2
公开(公告)日：2006-05-16
申请号：US10875052
申请日：2004-06-22
申请人： Sang Ick Lee , Jong Han Shin , Hyung Soon Park
发明人： Sang Ick Lee , Jong Han Shin , Hyung Soon Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：在衬底上形成栅极，在衬底的表面上形成接合区域，在衬底的所得结构上形成第一BPSG层，对第一BPSG层执行第一CVD工艺，形成第二BPSG 在第一BPSG层上形成着色插头接触，在所得衬底的所得结构上沉积多晶硅层，以及对多晶硅层，第二BPSG层和氮化物硬掩模执行第二CMP工艺。通过使用相对于氮化物层具有高抛光选择性的酸性浆料来进行CMP处理，从而消除了单元区域和外围区域之间的阶跃差异，从而简化了半导体制造工艺并消除了凹陷现象。

6. 发明申请

US20100210104A1 METHOD FOR FORMING COPPER WIRING IN A SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成铜线的方法
公开(公告)号：US20100210104A1
公开(公告)日：2010-08-19
申请号：US12427870
申请日：2009-04-22
申请人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
发明人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
IPC分类号： H01L21/768 , H01L21/306
CPC分类号： H01L21/02074 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.
摘要翻译：本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。该方法包括对经过CMP工艺形成铜线的铜层进行后清洗处理。后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

7. 发明授权

US08252686B2 Method for forming copper wiring in a semiconductor device 失效
标题翻译：在半导体器件中形成铜布线的方法
公开(公告)号：US08252686B2
公开(公告)日：2012-08-28
申请号：US12427870
申请日：2009-04-22
申请人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
发明人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/02074 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.
摘要翻译：本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。该方法包括在已经经过CMP工艺的铜层之后对铜层进行后清洗处理。后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

8. 发明授权

US07119015B2 Method for forming polysilicon plug of semiconductor device 有权
标题翻译：用于形成半导体器件的多晶硅插塞的方法
公开(公告)号：US07119015B2
公开(公告)日：2006-10-10
申请号：US10879220
申请日：2004-06-30
申请人： Hyung Soon Park , Min Suk Lee , Sang Ick Lee , Hyun Chul Sohn
发明人： Hyung Soon Park , Min Suk Lee , Sang Ick Lee , Hyun Chul Sohn
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/7684
摘要： Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.
摘要翻译：公开了一种用于形成半导体器件的多晶硅插塞的方法。该方法包括以下步骤：在包括单元区域和外围电路区域的半导体衬底上形成字线和硬掩模膜的堆叠图案; 在所述堆叠图案的侧壁上形成间隔物; 在半导体衬底上形成层间绝缘膜; 通过使用硬掩模膜作为抛光阻挡膜的CMP工艺来研磨层间绝缘膜; 在包括层间绝缘膜的半导体衬底上形成阻挡膜; 选择性地蚀刻阻挡膜和层间绝缘膜以形成着陆塞接触孔; 在所述半导体衬底上沉积填充所述着地插头接触孔的多晶硅膜; 使用阻挡膜作为蚀刻阻挡膜对多晶硅膜进行绝缘蚀刻; 并使用硬掩模膜作为抛光阻挡膜研磨多晶硅膜和阻挡膜以形成多晶硅插塞。

9. 发明授权

US06622580B1 Backlash-free speed reducing device 失效
标题翻译：无间隙减速装置
公开(公告)号：US06622580B1
公开(公告)日：2003-09-23
申请号：US09784348
申请日：2001-02-16
申请人： Pyung Hun Chang , Ju Yi Park , Hyung Soon Park , Je Hyung Jung , Bo Kyoung Jeon
发明人： Pyung Hun Chang , Ju Yi Park , Hyung Soon Park , Je Hyung Jung , Bo Kyoung Jeon
IPC分类号： F16H1900
CPC分类号： F16H19/005 , F16H57/12 , Y10T74/1836 , Y10T74/19623
摘要： A backlash-free speed reducing device includes a drive unit, a rotary unit, and a power output unit. The drive unit consists of a drive motor having a drive shaft. A first power transmission cable is wound around the drive shaft. The rotary unit has two first cylinders, with the first transmission cable fixed to the external surface of the first cylinders at opposite ends thereof and wound around or unwound from the first cylinders in response to a rotation of the drive shaft. Each of the first cylinders is concentrically fitted over a rotating shaft such that the first cylinders are linearly movable along the rotating shafts in opposite directions. A second power transmission cable is fixed to the external surfaces of the rotating shafts of the two first cylinders at opposite ends thereof. The power output unit has a second cylinder, with the second transmission cable wound around the second cylinder. This second cylinder is concentrically fitted over a power output shaft such that the cylinder is linearly movable along the power output shaft. The two power transmission cables thus maintain desired tension during an operation of the speed reducing device for achieving a high speed reduction ration, and so it is possible to prevent a backlash of the cables during such operation.
摘要翻译：无间隙减速装置包括驱动单元，旋转单元和功率输出单元。驱动单元由具有驱动轴的驱动马达组成。第一传动电缆缠绕在驱动轴上。旋转单元具有两个第一气缸，其中第一传动缆索在其相对端处固定到第一气缸的外表面，并且响应于驱动轴的旋转而缠绕在第一气缸上或从第一气缸展开。每个第一气缸同心地安装在旋转轴上，使得第一气缸沿着相反方向的旋转轴线性移动。第二电力传输电缆固定到两个第一气缸的旋转轴的外表面的相对端。动力输出单元具有第二气缸，第二传动缆索缠绕在第二气缸上。该第二气缸同心地安装在动力输出轴上，使得气缸沿动力输出轴线性移动。因此，在用于实现高速减速比的减速装置的操作期间，两个动力传动电缆保持期望的张力，因此可以防止在这种操作期间电缆的间隙。

10. 发明授权

US06723655B2 Methods for fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06723655B2
公开(公告)日：2004-04-20
申请号：US10180201
申请日：2002-06-25
申请人： Hyung Soon Park , Jong Goo Jung
发明人： Hyung Soon Park , Jong Goo Jung
IPC分类号： H01L21302
CPC分类号： H01L27/11521 , H01L21/31053 , H01L21/3212 , H01L21/76819 , H01L21/7684 , Y10S438/959
摘要： The present invention discloses methods for fabricating a semiconductor device. In one embodiment, a conductive interconnection is formed on a semiconductor substrate to overlap with a mask insulating film pattern. An insulating film spacer is formed at side walls of the pattern, a high temperature oxide layer is formed on the resultant structure, and an interlayer insulating film is formed on the HTO film to planarize the surface of the resultant structure. Storage electrode and bit line contact holes are formed to expose the semiconductor substrate, by etching the interlayer insulating film according to a photolithography process using a contact mask. A landing plug poly is formed by depositing a conductive layer for a contact plug to fill up the contact holes. A first CMP process for etching the conductive layer and the interlayer insulating film by a predetermined thickness is performed using a basic slurry, and a second CMP process of polishing the conductive layer for a contact plug and the interlayer insulating film by using a acid slurry is performed to expose the upper portion of the mask insulating film pattern, thereby forming the contact plug.
摘要翻译：本发明公开了半导体器件的制造方法。在一个实施例中，导电互连形成在半导体衬底上以与掩模绝缘膜图案重叠。在图案的侧壁上形成绝缘膜间隔物，在所得结构上形成高温氧化物层，在HTO膜上形成层间绝缘膜，使所得结构的表面平坦化。通过使用接触掩模根据光刻工艺蚀刻层间绝缘膜，形成存储电极和位线接触孔以暴露半导体衬底。通过沉积用于接触塞的导电层来填充接触孔来形成着陆塞多晶。使用碱性浆料进行用于蚀刻导电层和层间绝缘膜预定厚度的第一CMP工艺，并且通过使用酸浆料研磨用于接触塞的导电层和层间绝缘膜的第二CMP工艺是进行以露出掩模绝缘膜图案的上部，从而形成接触插塞。

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