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1. 发明授权

US08039347B2 Semiconductor device having vertically aligned pillar structures that have flat side surfaces and method for manufacturing the same 有权
标题翻译：具有垂直排列的具有平坦侧表面的柱结构的半导体器件及其制造方法
公开(公告)号：US08039347B2
公开(公告)日：2011-10-18
申请号：US12491565
申请日：2009-06-25
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim , Young Ju Lee
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim , Young Ju Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L29/66666
摘要： A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures.
摘要翻译：提出了具有由具有平坦侧表面的柱结构制成的垂直排列的晶体管的半导体器件。半导体器件包括半导体衬底，间隔物和栅极。半导体衬底具有平坦的侧表面的柱结构。间隔物仅在支柱结构的上部的侧壁上。门围绕柱结构的下部。

2. 发明授权

US07871913B2 Method for manufacturing semiconductor device having vertical transistor 有权
标题翻译：具有垂直晶体管的半导体器件的制造方法
公开(公告)号：US07871913B2
公开(公告)日：2011-01-18
申请号：US12335668
申请日：2008-12-16
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66666 , H01L29/4236 , H01L29/42376 , H01L29/7827
摘要： A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
摘要翻译：一种制造具有垂直晶体管的半导体器件的方法包括：在半导体衬底上形成硬掩模以暴露半导体衬底的部分。然后蚀刻半导体衬底的暴露部分以在半导体衬底中限定凹槽。在硬掩模和凹槽的表面上形成栅极导电层至不完全填充凹槽的厚度。牺牲层形成在栅极导电层上以完全填充凹槽。去除牺牲层的部分厚度以露出栅极导电层，并且去除形成在硬掩模上的栅极导电层的部分以及沟槽上部的侧壁上的部分。剩余的牺牲层被完全去除。通过蚀刻栅极导电层在栅极的下部的侧壁上形成栅极。

3. 发明授权

US08384135B2 Phase-change random access memory device and method of manufacturing the same 有权
标题翻译：相变随机存取存储器件及其制造方法
公开(公告)号：US08384135B2
公开(公告)日：2013-02-26
申请号：US13164490
申请日：2011-06-20
申请人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
发明人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：相变随机存取存储器件包括半导体衬底，形成在半导体衬底上的底部电极结构，包括与底部电极接触的导电材料层的圆柱形底部电极接触和圆柱形相变与底部电极接触的材料层。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

4. 发明申请

US20110240950A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：相变随机访问存储器件及其制造方法
公开(公告)号：US20110240950A1
公开(公告)日：2011-10-06
申请号：US13164490
申请日：2011-06-20
申请人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
发明人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：相变随机存取存储器件包括半导体衬底，形成在半导体衬底上的底部电极结构，包括与底部电极接触的导电材料层的圆柱形底部电极接触和圆柱形相变与底部电极接触的材料层。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

5. 发明授权

US08252686B2 Method for forming copper wiring in a semiconductor device 失效
标题翻译：在半导体器件中形成铜布线的方法
公开(公告)号：US08252686B2
公开(公告)日：2012-08-28
申请号：US12427870
申请日：2009-04-22
申请人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
发明人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/02074 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.
摘要翻译：本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。该方法包括在已经经过CMP工艺的铜层之后对铜层进行后清洗处理。后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

6. 发明申请

US20100210104A1 METHOD FOR FORMING COPPER WIRING IN A SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成铜线的方法
公开(公告)号：US20100210104A1
公开(公告)日：2010-08-19
申请号：US12427870
申请日：2009-04-22
申请人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
发明人： Hyung Soon Park , Noh Jung Kwak , Seung Jin Yeom , Choon Kun Ryu , Jong Goo Jung , Sung Jun Kim
IPC分类号： H01L21/768 , H01L21/306
CPC分类号： H01L21/02074 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.
摘要翻译：本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。该方法包括对经过CMP工艺形成铜线的铜层进行后清洗处理。后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

7. 发明申请

US20100215293A1 AIR BAG WITH PRESSURIZATION SPACE 审中-公开
标题翻译：带加压空间的气囊
公开(公告)号：US20100215293A1
公开(公告)日：2010-08-26
申请号：US12598784
申请日：2008-11-26
申请人： Sung Jun Kim
发明人： Sung Jun Kim
IPC分类号： B65D30/14
CPC分类号： B65D81/03
摘要： An air bag includes two inner sheets facing each other, two outer sheets located at an outer side of the two inner sheets, heat resistance material located at an inner side of any one inner sheet, a first thermal bonding line thermally bonding the two outer sheets to form air input channel, a second thermal bonding line thermally bonding the inner and outer sheets along the material with gap from the first thermal bonding line, and third thermal bonding lines extending from the second thermal bonding line oppositely to the air input channel to form air pillars, a second thermal bonding portion being formed to cross the third thermal bonding lines to thermally bond the two inner and outer sheets to form a pressurization space between the second thermal bonding portion and line, and the second thermal bonding portion being spaced apart from adjacent second thermal bonding portion to form a second passage.
摘要翻译：气囊包括彼此相对的两个内部片，位于两个内部片的外侧的两个外部片，位于任何一个内部片的内侧的耐热材料，热粘合两个外部片的第一热粘合线形成空气输入通道，第二热粘合线沿着与第一热粘合线间隙的材料热粘合内部和外部薄片，以及从第二热粘合线与空气输入通道相反地延伸的第三热粘合线，以形成空气柱，第二热粘合部分形成为穿过第三热粘合线以热粘合两个内部和外部薄片，以在第二热粘合部分和管线之间形成加压空间，并且第二热粘合部分与第二热粘合部分间隔开相邻的第二热粘合部分以形成第二通道。

8. 发明授权

US07621539B2 Actuator for AGCS of vehicle 有权
标题翻译：车辆AGCS执行机构
公开(公告)号：US07621539B2
公开(公告)日：2009-11-24
申请号：US11648438
申请日：2006-12-29
申请人： Hae Ryong Choi , Un Koo Lee , Sang Ho Lee , Hyun Sung , Jung Won Kim , Sung Jun Kim , Young Kwang Kim , In Ho Lee
发明人： Hae Ryong Choi , Un Koo Lee , Sang Ho Lee , Hyun Sung , Jung Won Kim , Sung Jun Kim , Young Kwang Kim , In Ho Lee
IPC分类号： B60G7/04 , B60G17/016 , F16C19/32 , F16C23/00
CPC分类号： B60G17/0155 , B60G7/006 , B60G2200/44 , B60G2202/422 , Y10T74/1868
摘要： The present invention provides an actuator for AGCS of a vehicle having a piston reciprocating rectilinearly, a screw bar engaged with the rear portion of the piston and rotating in place, and a drive motor rotating the screw bar in place, the actuator comprising an impact buffering means for buffering a load in the axial direction and an impact absorbing means for absorbing a load in the vertical direction to the axis, the impact buffering means and impact absorbing means being provided on the boundary portion between the screw bar and the motor.
摘要翻译：本发明提供了一种具有活塞往复直线运动的车辆的AGCS致动器，与活塞的后部接合并旋转就位的螺杆以及将螺杆转动就位的驱动马达，该致动器包括冲击缓冲用于沿轴向缓冲负载的装置和用于吸收沿着垂直于轴线的负载的冲击吸收装置，冲击缓冲装置和冲击吸收装置设置在螺杆与电动机之间的边界部分上。

9. 发明申请

US20130154790A1 CHIP RESISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：芯片电阻及其制造方法
公开(公告)号：US20130154790A1
公开(公告)日：2013-06-20
申请号：US13441596
申请日：2012-04-06
申请人： Jang Ho Park , Young Key Kim , Ki Won Suh , Jang Seok Yun , Jin Man Han , Sung Jun Kim
发明人： Jang Ho Park , Young Key Kim , Ki Won Suh , Jang Seok Yun , Jin Man Han , Sung Jun Kim
IPC分类号： H01C1/012 , H01C17/00
CPC分类号： H01C7/18 , H01C17/065 , H01C17/06526
摘要： There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).
摘要翻译：提供了包括陶瓷基板的芯片电阻器; 形成在所述陶瓷基板上并且包括第一导电金属和第一玻璃的第一电阻层; 以及形成在第一电阻层上的第二电阻层，包括第二导电金属和第二玻璃，并且具有比第一电阻层更小的玻璃含量，从而获得相对低的电阻和相对较小的电阻温度系数（TCR ）。

10. 发明授权

US07833908B2 Slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect and method for planarizing surface of semiconductor device using the same 有权
标题翻译：用于补偿纳米形貌效果的化学机械抛光的浆料组合物及使用其的半导体器件的平坦化表面的方法
公开(公告)号：US07833908B2
公开(公告)日：2010-11-16
申请号：US10556377
申请日：2004-05-11
申请人： Jea Gun Park , Takeo Katoh , Won Mo Lee , Hyun Goo Kang , Sung Jun Kim , Un Gyu Paik
发明人： Jea Gun Park , Takeo Katoh , Won Mo Lee , Hyun Goo Kang , Sung Jun Kim , Un Gyu Paik
IPC分类号： H01L21/302
CPC分类号： C09G1/02 , H01L21/31053
摘要： A slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect present on the surface of a wafer, and a method for planarizing the surface of a semiconductor device that utilizes the same are disclosed. The slurry composition of the present invention is aimed at compensating the nanotopography effect during chemical mechanical polishing process of the oxide layer formed on the surface of the wafer, and contains abrasive particles and an additive, wherein the size of the abrasive particles and the concentration of the additive are controlled within predetermined ranges in order to control the deviation of thickness (OTD) of the oxide layer below a certain level after the chemical mechanical polishing process.
摘要翻译：公开了一种能够补偿晶片表面上存在的纳米形貌效应的用于化学机械抛光的浆料组合物，以及用于平面化利用其的半导体器件的表面的方法。本发明的浆料组合物旨在补偿在晶片表面形成的氧化物层的化学机械抛光过程中的纳米形貌作用，并且包含磨料颗粒和添加剂，其中磨料颗粒的尺寸和浓度将添加剂控制在预定范围内，以便在化学机械抛光处理之后控制氧化物层的厚度（OTD）低于一定水平的偏差。

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