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1. 发明授权

US08039347B2 Semiconductor device having vertically aligned pillar structures that have flat side surfaces and method for manufacturing the same 有权
标题翻译：具有垂直排列的具有平坦侧表面的柱结构的半导体器件及其制造方法
公开(公告)号：US08039347B2
公开(公告)日：2011-10-18
申请号：US12491565
申请日：2009-06-25
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim , Young Ju Lee
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim , Young Ju Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L29/66666
摘要： A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures.
摘要翻译：提出了具有由具有平坦侧表面的柱结构制成的垂直排列的晶体管的半导体器件。半导体器件包括半导体衬底，间隔物和栅极。半导体衬底具有平坦的侧表面的柱结构。间隔物仅在支柱结构的上部的侧壁上。门围绕柱结构的下部。

2. 发明授权

US07871913B2 Method for manufacturing semiconductor device having vertical transistor 有权
标题翻译：具有垂直晶体管的半导体器件的制造方法
公开(公告)号：US07871913B2
公开(公告)日：2011-01-18
申请号：US12335668
申请日：2008-12-16
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66666 , H01L29/4236 , H01L29/42376 , H01L29/7827
摘要： A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
摘要翻译：一种制造具有垂直晶体管的半导体器件的方法包括：在半导体衬底上形成硬掩模以暴露半导体衬底的部分。然后蚀刻半导体衬底的暴露部分以在半导体衬底中限定凹槽。在硬掩模和凹槽的表面上形成栅极导电层至不完全填充凹槽的厚度。牺牲层形成在栅极导电层上以完全填充凹槽。去除牺牲层的部分厚度以露出栅极导电层，并且去除形成在硬掩模上的栅极导电层的部分以及沟槽上部的侧壁上的部分。剩余的牺牲层被完全去除。通过蚀刻栅极导电层在栅极的下部的侧壁上形成栅极。

3. 发明授权

US08384135B2 Phase-change random access memory device and method of manufacturing the same 有权
标题翻译：相变随机存取存储器件及其制造方法
公开(公告)号：US08384135B2
公开(公告)日：2013-02-26
申请号：US13164490
申请日：2011-06-20
申请人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
发明人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：相变随机存取存储器件包括半导体衬底，形成在半导体衬底上的底部电极结构，包括与底部电极接触的导电材料层的圆柱形底部电极接触和圆柱形相变与底部电极接触的材料层。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

4. 发明申请

US20110240950A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：相变随机访问存储器件及其制造方法
公开(公告)号：US20110240950A1
公开(公告)日：2011-10-06
申请号：US13164490
申请日：2011-06-20
申请人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
发明人： Cheol Hwi Ryu , Hyung Soon Park , Jong Han Shin , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：相变随机存取存储器件包括半导体衬底，形成在半导体衬底上的底部电极结构，包括与底部电极接触的导电材料层的圆柱形底部电极接触和圆柱形相变与底部电极接触的材料层。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

5. 发明授权

US07045450B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07045450B2
公开(公告)日：2006-05-16
申请号：US10875052
申请日：2004-06-22
申请人： Sang Ick Lee , Jong Han Shin , Hyung Soon Park
发明人： Sang Ick Lee , Jong Han Shin , Hyung Soon Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：在衬底上形成栅极，在衬底的表面上形成接合区域，在衬底的所得结构上形成第一BPSG层，对第一BPSG层执行第一CVD工艺，形成第二BPSG 在第一BPSG层上形成着色插头接触，在所得衬底的所得结构上沉积多晶硅层，以及对多晶硅层，第二BPSG层和氮化物硬掩模执行第二CMP工艺。通过使用相对于氮化物层具有高抛光选择性的酸性浆料来进行CMP处理，从而消除了单元区域和外围区域之间的阶跃差异，从而简化了半导体制造工艺并消除了凹陷现象。

6. 发明授权

US06939759B2 Method for manufacturing capacitor of semiconductor device 失效
标题翻译：制造半导体器件电容器的方法
公开(公告)号：US06939759B2
公开(公告)日：2005-09-06
申请号：US10721093
申请日：2003-11-26
申请人： Jong Han Shin , Sang Ick Lee
发明人： Jong Han Shin , Sang Ick Lee
IPC分类号： H01L21/28 , H01L21/02 , H01L21/20 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10855 , H01L28/75
摘要： The present invention discloses method for manufacturing capacitor of semiconductor device wherein a bonding layer is exposed via etch-back process without using a contact hole mask. In accordance with the method of the present invention, an interlayer insulating film, a bonding layer and a hard mask layer are sequentially formed on a semiconductor substrate. The hard mask layer, the bonding layer and the interlayer insulating film are then etched to form a storage electrode contact hole. The storage electrode contact hole is partially filled to form a storage electrode contact plug and the remaining portion is filled with a barrier metal layer pattern. The hard mask layer is then removed and a storage electrode contacting the barrier metal layer pattern is then formed on the bonding layer.
摘要翻译：本发明公开了一种用于制造半导体器件的电容器的方法，其中通过蚀刻工艺暴露接合层而不使用接触孔掩模。根据本发明的方法，在半导体衬底上依次形成层间绝缘膜，接合层和硬掩模层。然后对硬掩模层，接合层和层间绝缘膜进行蚀刻以形成存储电极接触孔。存储电极接触孔部分地填充以形成存储电极接触插塞，其余部分填充有阻挡金属层图案。然后去除硬掩模层，然后在接合层上形成与阻挡金属层图案接触的存储电极。

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