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1. 发明授权

US09362168B2 Non-volatile memory device and method for manufacturing same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09362168B2
公开(公告)日：2016-06-07
申请号：US14150193
申请日：2014-01-08
申请人： Kabushiki Kaisha Toshiba
发明人： Toshiharu Tanaka
IPC分类号： G11C5/06 , H01L21/768 , H01L27/06 , H01L27/105
CPC分类号： H01L21/76897 , G11C5/06 , H01L27/0688 , H01L27/1052 , H01L29/78642
摘要： According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.
摘要翻译：根据一个实施例，非易失性存储器件包括设置在底层上的第一布线，设置在第一布线上并包括多个存储单元的第一存储单元阵列，第一选择元件包括第一控制电极，第一布线和第一存储单元阵列。该装置还包括与第一布线设置在与第一布线相同的电平并与第一控制电极电连接的第二布线，以及电连接第一控制电极和第二布线的第一插头，第一插头的一端与所述第二布线和所述第一插头的侧表面与所述第一控制电极接触。

2. 发明授权

US09704922B2 Semiconductor memory device and method of manufacturing the same while avoiding process damage to a variable resistance film 有权
公开(公告)号：US09704922B2
公开(公告)日：2017-07-11
申请号：US14850527
申请日：2015-09-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsushi Oga , Mutsumi Okajima , Takeshi Yamaguchi , Hiroyuki Ode , Toshiharu Tanaka , Natsuki Fukuda
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/249 , H01L45/08 , H01L45/085 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/1675 , H01L45/1683
摘要： According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

3. 发明授权

US09418737B2 Nonvolatile semiconductor memory device and method of controlling the same 有权
标题翻译：非易失性半导体存储器件及其控制方法
公开(公告)号：US09418737B2
公开(公告)日：2016-08-16
申请号：US14813523
申请日：2015-07-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takeshi Takagi , Masaki Yamato , Hiroyuki Ode , Takeshi Yamaguchi , Toshiharu Tanaka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0064 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0083 , G11C2013/0092 , G11C2213/71
摘要： A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列; 以及控制电路，其控制施加到该存储单元阵列的电压。存储单元阵列包括：第一布线; 与第一布线相交的第二布线; 以及设置在这些线的相交处并包括可变电阻元件的存储单元。在存储单元的重写操作中，控制电路重复执行脉冲施加操作和验证操作，向存储单元施加脉冲电压的脉冲施加操作以及向存储器单元施加第一电压的校验操作以确定重写操作是否已经完成。控制电路被配置为在来自存储器单元的读取操作中向存储单元施加第二电压。第二电压具有大于第一电压的电压值。

4. 发明授权

US09559300B2 Resistive random access memory device and manufacturing method thereof 有权
标题翻译：电阻随机存取存储器件及其制造方法
公开(公告)号：US09559300B2
公开(公告)日：2017-01-31
申请号：US14472670
申请日：2014-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroyuki Ode , Takeshi Yamaguchi , Takeshi Takagi , Toshiharu Tanaka , Masaki Yamato
IPC分类号： H01L27/10 , H01L45/00 , G11C13/00 , G11C11/419 , H01L27/118 , H01L27/115 , H01L27/24 , H01L27/112
CPC分类号： H01L45/146 , G11C11/419 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01L27/11206 , H01L27/115 , H01L27/118 , H01L27/24 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/16
摘要： In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
摘要翻译：根据实施例，电阻随机存取存储器件包括衬底，第一和第二布线以及存储单元。第一和第二布线被布置在基板上以便彼此相交。存储单元设置在第一和第二布线之间的第一和第二布线的交点处，并且包括第一电极，第一电极上的电阻切换膜，电阻开关膜上的第二电极和氧化钽（TaOx）层。第一电极电连接到第一布线。第二电极电连接到第二布线。氧化钽（TaOx）层设置在第一电极和电阻开关膜之间并与电阻开关膜接触。

5. 发明授权

US09543002B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09543002B2
公开(公告)日：2017-01-10
申请号：US14840312
申请日：2015-08-31
申请人： Kabushiki Kaisha Toshiba
发明人： Toshiharu Tanaka
IPC分类号： H01L27/24 , H01L23/528 , G11C13/00
CPC分类号： G11C13/0021 , G11C13/003 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/249
摘要： The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor layer. The memory cell array comprises a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction. The wiring line layer comprises: a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction; and a second connecting wiring line connected to a second select gate line adjacent in a second direction to the first select gate line. This second connecting wiring line at least comprises: a first portion extending in the third direction; and a second portion extending from the first portion to a layer below the first connecting wiring line.
摘要翻译：晶体管层设置在存储层的上方或下方，并且包括晶体管。布线层连接存储层和晶体管层。存储单元阵列包括连接到在第三方向上排列的多个选择晶体管的栅极的多个选择栅极线。所述布线层包括：连接到所述多个选择栅极线中的第一选择栅极线并沿第三方向延伸的第一连接布线; 以及连接到与第一选择栅极线在第二方向相邻的第二选择栅极线的第二连接布线。该第二连接布线至少包括：沿第三方向延伸的第一部分; 以及从第一部分延伸到第一连接布线下方的第二部分。

6. 发明申请

US20160019959A1 NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20160019959A1
公开(公告)日：2016-01-21
申请号：US14635448
申请日：2015-03-02
申请人： Kabushiki Kaisha Toshiba
发明人： Takeshi TAKAGI , Masaki Yamato , Hiroyuki Ode , Takeshi Yamaguchi , Toshiharu Tanaka
IPC分类号： G11C13/00 , G06F11/07
CPC分类号： G11C13/0069 , G06F11/073 , G06F11/076 , G06F11/0793 , G11C13/0007 , G11C13/0064 , G11C13/0097 , G11C2013/0092 , G11C2213/71
摘要： A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
摘要翻译：非易失性存储器件包括存储单元，该存储单元包括连接在一对布线之间的可变电阻元件和在连接到存储单元的布线对之间施加电压的控制电路。在数据重写中，控制电路重复第一电压施加步骤，在所述布线对之间施加第一写入电压，以及第一验证步骤，在所述布线对之间施加低于所述第一写入电压的第一电压，并且比较电池电流通过具有第一阈值电流的单元，重复步骤，直到单元电流和第一阈值电流的大小关系满足第一条件。如果满足第一条件，则电路执行施加第二写入电压在两对布线之间的第二电压施加步骤。

7. 发明授权

US09166164B2 Method for manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device 有权
标题翻译：用于制造非易失性半导体存储装置和非易失性半导体存储装置的方法
公开(公告)号：US09166164B2
公开(公告)日：2015-10-20
申请号：US14482893
申请日：2014-09-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toshiharu Tanaka
IPC分类号： H01L21/00 , H01L45/00 , H01L27/102 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/1021 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.
摘要翻译：根据实施例的非易失性半导体存储装置的制造方法包括将在第一方向上延伸的第一线和由金属材料制成的可变电阻元件的膜层叠在半导体基板上，在所述第一方向和第二方向上将形成为所述可变电阻元件的所述膜分割成多个片段，在所述多个片段之间形成层间绝缘膜，所述层间绝缘膜通过将制成所述可变电阻元件的膜沿第二方向并且将制成的可变电阻元件的膜的金属材料氧化，并且将在第二方向上延伸的上电极和第二电极按顺序层叠在制成可变电阻元件的膜和层间绝缘膜上。

8. 发明授权

US09721961B2 Semiconductor memory device 有权
公开(公告)号：US09721961B2
公开(公告)日：2017-08-01
申请号：US14970082
申请日：2015-12-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mutsumi Okajima , Atsushi Oga , Takeshi Yamaguchi , Hiroyuki Ode , Toshiharu Tanaka , Natsuki Fukuda
IPC分类号： H01L27/24 , H01L45/00 , H01L27/11565
CPC分类号： H01L27/11565 , H01L27/2427 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1253 , H01L45/16
摘要： In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

9. 发明授权

US09336880B2 Nonvolatile memory device and method of controlling the same 有权
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US09336880B2
公开(公告)日：2016-05-10
申请号：US14635448
申请日：2015-03-02
申请人： Kabushiki Kaisha Toshiba
发明人： Takeshi Takagi , Masaki Yamato , Hiroyuki Ode , Takeshi Yamaguchi , Toshiharu Tanaka
IPC分类号： G11C13/00 , G06F11/07
CPC分类号： G11C13/0069 , G06F11/073 , G06F11/076 , G06F11/0793 , G11C13/0007 , G11C13/0064 , G11C13/0097 , G11C2013/0092 , G11C2213/71
摘要： A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
摘要翻译：非易失性存储器件包括存储单元，该存储单元包括连接在一对布线之间的可变电阻元件和在连接到存储单元的布线对之间施加电压的控制电路。在数据重写中，控制电路重复第一电压施加步骤，在所述布线对之间施加第一写入电压，以及第一验证步骤，在所述布线对之间施加低于所述第一写入电压的第一电压，并且比较电池电流通过具有第一阈值电流的单元，重复步骤，直到单元电流和第一阈值电流的大小关系满足第一条件。如果满足第一条件，则电路执行施加第二写入电压在两对布线之间的第二电压施加步骤。

10. 发明申请

US20150083989A1 RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：电阻随机访问存储器件及其制造方法
公开(公告)号：US20150083989A1
公开(公告)日：2015-03-26
申请号：US14472670
申请日：2014-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroyuki ODE , Takeshi Yamaguchi , Takeshi Takagi , Toshiharu Tanaka , Masaki Yamato
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , G11C11/419 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01L27/11206 , H01L27/115 , H01L27/118 , H01L27/24 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/16
摘要： In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
摘要翻译：根据实施例，电阻随机存取存储器件包括衬底，第一和第二布线以及存储单元。第一和第二布线被布置在基板上以便彼此相交。存储单元设置在第一和第二布线之间的第一和第二布线的交点处，并且包括第一电极，第一电极上的电阻切换膜，电阻开关膜上的第二电极和氧化钽（TaOx）层。第一电极电连接到第一布线。第二电极电连接到第二布线。氧化钽（TaOx）层设置在第一电极和电阻开关膜之间并与电阻开关膜接触。

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