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1. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

2. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

3. 发明申请

US20110103152A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110103152A1
公开(公告)日：2011-05-05
申请号：US13004926
申请日：2011-01-12
申请人： Masahiro YOSHIHARA , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro YOSHIHARA , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

4. 发明授权

US08107293B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08107293B2
公开(公告)日：2012-01-31
申请号：US13004926
申请日：2011-01-12
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

5. 发明授权

US07881120B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07881120B2
公开(公告)日：2011-02-01
申请号：US12408260
申请日：2009-03-20
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

6. 发明申请

US20080291743A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20080291743A1
公开(公告)日：2008-11-27
申请号：US12123791
申请日：2008-05-20
申请人： Toshiaki Edahiro , Masahiro Yoshihara
发明人： Toshiaki Edahiro , Masahiro Yoshihara
IPC分类号： G11C16/24 , G11C16/26
CPC分类号： G11C16/32 , G11C16/26
摘要： This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.
摘要翻译：本公开涉及包括位线的半导体存储装置; 向电池提供电荷的第一电容器; 第一感测节点发送对应于所述小区的数据的电位; 对位线充电的第一预充电部分，第一电容器和第一感测节点; 锁定数据的第一锁存部分; 第一感测部分，包括连接在电源和第一锁存部分之间的第一感测晶体管，栅极连接到第一感测节点; 以及将第一锁存部分和第一检测晶体管之间的第一节点连接到位线的第一钳位部分，其中第一电容器在检测期间将电荷提供给位线，并且第一感测部分从电源提供电荷响应于第一感测节点处的电位，经由第一钳位部分到位线。

7. 发明授权

US07692987B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07692987B2
公开(公告)日：2010-04-06
申请号：US12123791
申请日：2008-05-20
申请人： Toshiaki Edahiro , Masahiro Yoshihara
发明人： Toshiaki Edahiro , Masahiro Yoshihara
IPC分类号： G11C7/00
CPC分类号： G11C16/32 , G11C16/26
摘要： This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.
摘要翻译：本公开涉及包括位线的半导体存储装置; 向电池提供电荷的第一电容器; 第一感测节点发送对应于所述小区的数据的电位; 对位线充电的第一预充电部分，第一电容器和第一感测节点; 锁定数据的第一锁存部分; 第一感测部分，包括连接在电源和第一锁存部分之间的第一感测晶体管，栅极连接到第一感测节点; 以及将第一锁存部分和第一检测晶体管之间的第一节点连接到位线的第一钳位部分，其中第一电容器在检测期间将电荷提供给位线，并且第一感测部分从电源提供电荷响应于第一感测节点处的电位，经由第一钳位部分到位线。

8. 发明申请

US20090244978A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090244978A1
公开(公告)日：2009-10-01
申请号：US12408260
申请日：2009-03-20
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

9. 发明授权

US08325545B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08325545B2
公开(公告)日：2012-12-04
申请号：US13234760
申请日：2011-09-16
申请人： Toshiaki Edahiro
发明人： Toshiaki Edahiro
IPC分类号： G11C7/00
CPC分类号： G11C16/3459 , G11C16/0483
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line connected to the memory cells, and a control circuit. In a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列，存储单元的阈值电压在擦除状态下被设置为最低，并且根据程序状态中的数据顺序地设置更高的位置，连接到存储器单元的多个位线连接到存储单元的字线，以及控制电路。在第一存储器单元被编程为处于编程状态的阈值电压中最低的第一阈值电压的情况下，控制电路被配置为将连接到第一存储单元的第一位线充电到第一存储单元之间的第三电压当存储器单元被编程到高于第一阈值电压的第二阈值电压时施加到位线的电压，以及当禁止存储器单元被编程时施加到位线的第二电压。

10. 发明授权

US07907463B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07907463B2
公开(公告)日：2011-03-15
申请号：US12478181
申请日：2009-06-04
申请人： Toshiaki Edahiro , Fumitaka Arai
发明人： Toshiaki Edahiro , Fumitaka Arai
IPC分类号： G11C7/00
CPC分类号： G11C16/16 , G11C16/0483
摘要： A controller repeats an erase operation, an erase verify operation, and a step-up operation. A first storage unit stores a value of an erase start voltage applied first as an erase voltage when a series of erase operations are executed. A second storage unit stores a value of an erase completion voltage which is an erase voltage when erasure of data is finished in the erase operation and the erase verify operation. A first comparator compares the erase completion voltage with the erase start voltage each time the erase operation is executed. When the first comparator determines that the erase completion voltage is larger than the erase start voltage, a counter counts up a count value. When the count value becomes larger than a predetermined value, a second comparator updates a value of the erase start voltage stored in the first storage unit.
摘要翻译：控制器重复擦除操作，擦除验证操作和升压操作。当执行一系列擦除操作时，第一存储单元存储首先施加的擦除开始电压作为擦除电压的值。第二存储单元存储在擦除操作和擦除验证操作中擦除数据结束时作为擦除电压的擦除完成电压的值。每次执行擦除操作时，第一比较器将擦除完成电压与擦除开始电压进行比较。当第一比较器确定擦除完成电压大于擦除开始电压时，计数器对计数值进行计数。当计数值变得大于预定值时，第二比较器更新存储在第一存储单元中的擦除开始电压的值。

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