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1. 发明授权

US08711635B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08711635B2
公开(公告)日：2014-04-29
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译：非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压验证操作。

2. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

3. 发明授权

US08482985B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08482985B2
公开(公告)日：2013-07-09
申请号：US13315516
申请日：2011-12-09
申请人： Ayako Yamano , Osamu Nagao , Toshiaki Edahiro
发明人： Ayako Yamano , Osamu Nagao , Toshiaki Edahiro
IPC分类号： G11C16/06
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3409 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.
摘要翻译：根据实施例的非易失性半导体存储装置包括执行擦除序列的擦除电路，其中在擦除序列中，擦除电路执行：在擦除操作之后将选择存储单元组改变为擦除状态的擦除操作，对选择存储单元组进行软编程操作以解决过擦除状态，并且在软编程操作之后，对第一部分选择存储单元组和第二部分选择存储单元组的至少一个部分选择存储单元组执行第一软程序验证操作部分选择存储单元组，以确认部分选择存储单元组是否包括具有等于或大于预定第一阈值的阈值的预定数量的存储单元或更多个，以及在第一软程序验证操作之后。

4. 发明申请

US20130010541A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130010541A1
公开(公告)日：2013-01-10
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

5. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

6. 发明授权

US08000155B2 Non-volatile memory device and method for writing data thereto 有权
公开(公告)号：US08000155B2
公开(公告)日：2011-08-16
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C7/22 , G11C7/06 , G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

7. 发明授权

US07495963B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07495963B2
公开(公告)日：2009-02-24
申请号：US11692501
申请日：2007-03-28
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C2211/5621 , G11C2216/14
摘要： A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile memory cells arranged, memory cells in the main parts serving as information cells used for storing data, the remaining parts as reference cells used for driving a reference current; three or more bit line pairs disposed in the first and second cell arrays, respectively; a sense amplifier so shared by the bit line pairs as to sequentially detect cell current differences between the information cells and the reference cells coupled to the bit line pairs; and first and second data latches arranged to store write data to be written into the first and second cell arrays, each number of the first and second data latches being equal to that of the bit line pairs, which share the sense amplifier and are simultaneously selected.
摘要翻译：半导体存储器件包括：第一和第二单元阵列，每个具有电可重写和非易失性存储单元，主要部分中的存储单元用作用于存储数据的信息单元，其余部分作为用于驱动参考电流的参考单元 ; 分别设置在第一和第二单元阵列中的三个或更多个位线对; 由位线对共享的读出放大器，以顺序地检测信息单元和耦合到位线对的参考单元之间的单元电流差; 以及第一和第二数据锁存器，被布置为存储要写入第一和第二单元阵列的写入数据，每个数量的第一和第二数据锁存器等于共享读出放大器并且被同时选择的位线对的数量。

8. 发明授权

US07486565B2 Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate 有权
标题翻译：具有各自包括电荷累积层和控制栅极的存储单元的半导体存储器件
公开(公告)号：US07486565B2
公开(公告)日：2009-02-03
申请号：US11613492
申请日：2006-12-20
申请人： Toshiaki Edahiro
发明人： Toshiaki Edahiro
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C7/14 , G11C7/18 , G11C16/0433 , G11C16/24 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell array, a bit line, a precharge circuit and a first sense amplifier. The memory cell array includes memory cells. The bit line connects commonly the memory cells in the same column. The precharge circuit applies a precharge potential to the bit line in reading data. The first sense amplifier amplifies data read onto the bit line. The precharge circuit determines the data read on the bit line using as a reference potential the precharge potential applied to the bit line by the precharge circuit.
摘要翻译：半导体存储器件包括存储单元阵列，位线，预充电电路和第一读出放大器。存储单元阵列包括存储单元。位线通常连接同一列中的存储单元。预充电电路在读取数据时向位线施加预充电电位。第一个读出放大器放大读取到位线上的数据。预充电电路使用预充电电路作为施加到位线的预充电电位作为参考电位来确定在位线上读取的数据。

9. 发明申请

US20080253181A1 METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于编程半导体存储器件的方法
公开(公告)号：US20080253181A1
公开(公告)日：2008-10-16
申请号：US12061105
申请日：2008-04-02
申请人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
发明人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.
摘要翻译：一种编程半导体存储器件的方法，该半导体存储器件包括这样的程序序列，将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制该程序序列以完成对多个存储器单元的编程，目标阈值水平的高度。

10. 发明申请

US20070147112A1 SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME 有权
标题翻译：具有相同功能的SENSE放大器和半导体存储器件
公开(公告)号：US20070147112A1
公开(公告)日：2007-06-28
申请号：US11563408
申请日：2006-11-27
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C7/02 , G11C16/06
CPC分类号： G11C7/065 , G11C16/28
摘要： A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.
摘要翻译：读出放大器包括：NMOS晶体管，其漏极耦合到输出节点，其栅极耦合到输出节点，其源极共同耦合到地电位节点; PMOS晶体管，其漏极耦合到NMOS晶体管的漏极，其源极耦合到输入节点; PMOS晶体管，其漏极耦合到输入节点，其栅极耦合到输出节点，其源极经由电流源装置耦合到电源节点; 并且设置在所述输出节点和所述接地电位节点之间的NMOS晶体管将在感测之前导通; 以及设置在输出节点之间的均衡晶体管。

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