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1. 发明申请

US20070246804A1 ORGANIC INSULATING FILM, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE USING SUCH ORGANIC INSULATING FILM AND MANUFACTURING METHOD THEREOF 有权
标题翻译：有机绝缘膜，其制造方法，使用这种有机绝缘膜的半导体器件及其制造方法
公开(公告)号：US20070246804A1
公开(公告)日：2007-10-25
申请号：US11534941
申请日：2006-09-25
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
IPC分类号： H01L23/52 , C07F7/04
CPC分类号： H01L21/7681 , C23C16/30 , C23C16/36 , C23C16/401 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3148 , H01L21/31633 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76808 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance. The present invention relates to an organic film made of one of SiOCH, SiCHN and SiCH that is formed using, as a source, a polyorganosilane whose C/Si ratio is at least 5 or greater and molecular weight is 100 or greater, and a semiconductor device wherein such an organic insulating film is used, and more particularly to a semiconductor device having a trench structure.
摘要翻译：目前被广泛研究的SiC和SiCN的介电常数分别为4.5〜5左右，SiOC为2.8〜3.0左右。随着器件尺寸减小引起的互连尺寸和互连间距的进一步小型化，出现了强烈的要求，即应进一步降低介电常数。此外，由于SiOC与SiCN的蚀刻选择比以及SiOC与SiC的蚀刻选择比小，因此如果使用SiCN或SiC作为蚀刻停止膜，则金属配线层的表面在光刻胶去除时可能被氧化，这导致高接触电阻的问题。本发明涉及使用以C / Si比为5以上且分子量为100以上的聚有机硅烷作为源的SiOCH，SiCHN和SiCH之一构成的有机膜，以及半导体使用这种有机绝缘膜的装置，更具体地说涉及具有沟槽结构的半导体器件。

2. 发明授权

US07910474B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07910474B2
公开(公告)日：2011-03-22
申请号：US12098190
申请日：2008-04-04
申请人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
发明人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L23/5222 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents, and, in particular, a low-carbon-concentration film 6a with a small carbon content is set to be a lower layer therein and a high-carbon-concentration film 6b with a large carbon content is set to be an upper layer therein, whereby the effectual prevention against the Cu diffusion, a high etching selection ratio and good adhesiveness to the Cu interconnection can be certainly provided by the presence of the low-carbon-concentration film 6a, while the overall dielectric constant can be well reduced by the presence of the high-carbon-concentration film 6b.
摘要翻译：本发明的目的是提供一种半导体器件，其包括其间的层间绝缘膜的蚀刻选择率高的阻挡膜，对Cu扩散的良好的预防功能，低介电常数和对Cu互连的优异粘合性及其制造方法。设置在互连或通孔插塞及其上覆层间绝缘膜之间的阻挡膜（例如，第二阻挡膜6）具有由多个含有硅和碳的膜（优选硅，碳和氮），具有不同的碳含量，特别是具有小碳含量的低碳浓度膜6a被设定为下层，并且具有大碳含量的高碳浓度膜6b为在其中设置为上层，由此通过低碳浓度膜6a的存在可以确定地提供对Cu扩散的有效防止，高的蚀刻选择率和对Cu互连的良好的粘合性，而整个电介质通过高碳浓度膜6b的存在可以很好地降低常数。

3. 发明授权

US07763979B2 Organic insulating film, manufacturing method thereof, semiconductor device using such organic insulating film and manufacturing method thereof 有权
标题翻译：有机绝缘膜及其制造方法，使用该有机绝缘膜的半导体装置及其制造方法
公开(公告)号：US07763979B2
公开(公告)日：2010-07-27
申请号：US11534941
申请日：2006-09-25
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
IPC分类号： H01L25/34
CPC分类号： H01L21/7681 , C23C16/30 , C23C16/36 , C23C16/401 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3148 , H01L21/31633 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76808 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced.Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.The present invention relates to an organic film made of one of SiOCH, SiCHN and SiCH that is formed using, as a source, a polyorganosilane whose C/Si ratio is at least 5 or greater and molecular weight is 100 or greater, and a semiconductor device wherein such an organic insulating film is used, and more particularly to a semiconductor device having a trench structure.
摘要翻译：目前被广泛研究的SiC和SiCN的介电常数分别为4.5〜5左右，SiOC为2.8〜3.0左右。随着器件尺寸减小引起的互连尺寸和互连间距的进一步小型化，出现了强烈的要求，即应进一步降低介电常数。此外，由于SiOC与SiCN的蚀刻选择比以及SiOC与SiC的蚀刻选择比小，因此如果使用SiCN或SiC作为蚀刻停止膜，则金属配线层的表面在光刻胶去除时可能被氧化，这导致高接触电阻的问题。本发明涉及使用以C / Si比为5以上且分子量为100以上的聚有机硅烷作为源的SiOCH，SiCHN和SiCH之一构成的有机膜，以及半导体使用这种有机绝缘膜的装置，更具体地说涉及具有沟槽结构的半导体器件。

4. 发明授权

US07391115B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07391115B2
公开(公告)日：2008-06-24
申请号：US10768676
申请日：2004-02-02
申请人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
发明人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L23/5222 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents, and, in particular, a low-carbon-concentration film 6a with a small carbon content is set to be a lower layer therein and a high-carbon-concentration film 6b with a large carbon content is set to be an upper layer therein, whereby the effectual prevention against the Cu diffusion, a high etching selection ratio and good adhesiveness to the Cu interconnection can be certainly provided by the presence of the low-carbon-concentration film 6a, while the overall dielectric constant can be well reduced by the presence of the high-carbon-concentration film 6b.
摘要翻译：本发明的目的是提供一种半导体器件，其包括其间的层间绝缘膜的蚀刻选择率高的阻挡膜，对Cu扩散的良好的预防功能，低介电常数和对Cu互连的优异粘合性及其制造方法。设置在互连或通孔插塞及其上覆层间绝缘膜之间的阻挡膜（例如，第二阻挡膜6）具有由多个含有硅和碳的膜（优选硅，碳和氮），具有不同的碳含量，特别是具有小碳含量的低碳浓度膜6a被设定为下层，并且具有大碳的高碳浓度膜6b 含量被设定为上层，由此可以通过低碳浓度膜6a的存在来确定地提供对Cu扩散的有效防止，高的蚀刻选择率和对Cu互连的良好的粘附性，同时通过存在高碳浓度膜6b可以很好地降低总介电常数。

5. 发明授权

US08399879B2 Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor 有权
标题翻译：纳米线场效应晶体管，晶体管的制造方法以及包括晶体管的集成电路
公开(公告)号：US08399879B2
公开(公告)日：2013-03-19
申请号：US12993880
申请日：2009-06-05
申请人： Yongxun Liu , Takashi Matsukawa , Kazuhiko Endo , Shinichi Ouchi , Kunihiro Sakamoto , Meishoku Masahara
发明人： Yongxun Liu , Takashi Matsukawa , Kazuhiko Endo , Shinichi Ouchi , Kunihiro Sakamoto , Meishoku Masahara
IPC分类号： H01L29/06 , H01L31/072 , H01L31/019 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.
摘要翻译：提供一种制造纳米线场效应晶体管的方法，包括以下步骤：制备具有（100）表面取向的SOI衬底和纳米线场效应晶体管，其中构成纳米线的两个三角柱形构件由在具有（100）表面的SOI衬底上，使三角柱状构件的棱线经由绝缘体面对，从而将硅晶体层彼此重叠地布置; 将构成SOI衬底的硅晶体加工成具有矩形横截面的立式板状构件; 并且作为纳米线，通过取向相关的湿法蚀刻将硅晶体加工成两个三角柱形部件一个在另一个上方布置的形状，使得构成纳米线的三角柱形部件的脊线面向通过脊线，以及包括纳米线场效应晶体管的集成电路。

6. 发明授权

US08040717B2 SRAM cell and SRAM device 有权
标题翻译： SRAM单元和SRAM器件
公开(公告)号：US08040717B2
公开(公告)日：2011-10-18
申请号：US12521408
申请日：2007-12-20
申请人： Shinichi Ouchi , Yongxun Liu , Meishoku Masahara , Takashi Matsukawa , Kazuhiko Endo
发明人： Shinichi Ouchi , Yongxun Liu , Meishoku Masahara , Takashi Matsukawa , Kazuhiko Endo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , H01L21/845 , H01L27/11 , H01L27/1211 , H01L29/785 , H01L29/7856
摘要： A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.
摘要翻译：静态随机存取存储器（SRAM）单元包括设置在基板上并且彼此平行布置的第一至第四半导体薄板。在相应的半导体薄板上形成具有第一导电类型的第一四端双栅场效应晶体管（FET），彼此串联连接的第二和第三四端双栅FET 具有彼此串联并具有第二导电类型的第二导电类型，第四和第五四端子双栅极FET以及具有第一导电类型的第六四端子双栅极FET。第三和第四四端子双栅极FET形成选择晶体管，第一，第二，第五和第六四端子双栅极FET形成互补的金属氧化物半导体（CMOS）反相器。

7. 发明授权

US07536153B2 Activation signal output circuit having multiple amplifier circuits 有权
标题翻译：激活信号输出电路具有多个放大电路
公开(公告)号：US07536153B2
公开(公告)日：2009-05-19
申请号：US10566614
申请日：2004-12-15
申请人： Hisanori Uda , Hiroaki Hayashi , Yoshiyuki Kago , Yukiomi Tanaka , Kazuhiko Endo
发明人： Hisanori Uda , Hiroaki Hayashi , Yoshiyuki Kago , Yukiomi Tanaka , Kazuhiko Endo
IPC分类号： H04B1/16
CPC分类号： H03F3/45085 , H03F3/189 , H03F3/3022 , H03F2200/54
摘要： With a capacitor C inserted in an interstage portion of multiple stages of amplifier circuits, a high pass filter is generated by the capacitor C and an input impedance |Z| of an amplifier circuit in the next stage. Accordingly, frequency components lower than a cutoff frequency fc are cut off, and therefore are not transferred to the subsequent stage. However, radio frequency components higher than or equal to a fundamental wave component determined by an envelope of a radio frequency signal intermittently transmitted can be transferred. Consequently, transfer of DC offset potentials can be cut off, and noise, such as flicker noise, having great power in a DC or near-DC zone can be effectively cut off. Thereby, the S/N ratio, detection sensitivity, and detection accuracy can be improved.
摘要翻译：通过将电容器C插入到多级放大器电路的级间部分中，由电容器C产生高通滤波器，并且输入阻抗| Z | 的放大器电路在下一阶段。因此，低于截止频率fc的频率分量被切断，因此不会转移到后续阶段。然而，可以传送高于或等于由间歇发送的射频信号的包络确定的基波分量的射频分量。因此，DC偏移电位的传递可以被切断，并且可以有效地切断在DC或近DC区域具有大功率的噪声，例如闪烁噪声。从而可以提高S / N比，检测灵敏度和检测精度。

8. 发明申请

US20060217099A1 Activation signal output circuit 有权
标题翻译：激活信号输出电路
公开(公告)号：US20060217099A1
公开(公告)日：2006-09-28
申请号：US10566614
申请日：2004-12-15
申请人： Hisanori Uda , Hiroaki Hayashi , Yoshiyuki Kago , Yukiomi Tanaka , Kazuhiko Endo
发明人： Hisanori Uda , Hiroaki Hayashi , Yoshiyuki Kago , Yukiomi Tanaka , Kazuhiko Endo
IPC分类号： H04B1/10
CPC分类号： H03F3/45085 , H03F3/189 , H03F3/3022 , H03F2200/54
摘要： With a capacitor C inserted in an interstage portion of multiple stages of amplifier circuits, a high pass filter is generated by the capacitor C and an input impedance |Z| of an amplifier circuit in the next stage. Accordingly, frequency components lower than a cutoff frequency fc are cut off, and therefore are not transferred to the subsequent stage. However, radio frequency components higher than or equal to a fundamental wave component determined by an envelope of a radio frequency signal intermittently transmitted can be transferred. Consequently, transfer of DC offset potentials can be cut off, and noise, such as flicker noise, having great power in a DC or near-DC zone can be effectively cut off. Thereby, the S/N ratio, detection sensitivity, and detection accuracy can be improved.
摘要翻译：通过将电容器C插入到多级放大器电路的级间部分中，由电容器C产生高通滤波器，并且输入阻抗| Z | 的放大器电路在下一阶段。因此，低于截止频率fc的频率分量被切断，因此不会转移到后续阶段。然而，可以传送高于或等于由间歇发送的射频信号的包络确定的基波分量的射频分量。因此，DC偏移电位的传递可以被切断，并且可以有效地切断在DC或近DC区域具有大功率的噪声，例如闪烁噪声。从而可以提高S / N比，检测灵敏度和检测精度。

9. 发明申请

US20060071654A1 Activation signal output circuit and determining circuit 失效
标题翻译：激活信号输出电路和确定电路
公开(公告)号：US20060071654A1
公开(公告)日：2006-04-06
申请号：US10536338
申请日：2003-11-26
申请人： Kazuo Mizuno , Ryu Kimura , Yoshiyuki Kago , Yukiomi Tanaka , Kazuhiko Endo , Hisanori Uda , Hiroaki Hayashi
发明人： Kazuo Mizuno , Ryu Kimura , Yoshiyuki Kago , Yukiomi Tanaka , Kazuhiko Endo , Hisanori Uda , Hiroaki Hayashi
IPC分类号： G01R25/00
CPC分类号： H03D1/10 , H03D1/18
摘要： A start signal output circuit having an RF/DC conversion circuit to which radio frequency power (RF) of specified frequency is inputted and from which a direct current potential (DC) is outputted, comprises a detection/amplification circuit 210 which includes a voltage doubler wave-detector circuit 10 configured including a sensing diode Q1 (Tr34) for sensing the RF power, a differential amplifier including differential pair transistors Tr31 and Tr32, and a current mirror circuit. A base current of one Tr31 of the differential pair transistors is brought into substantial agreement with a DC component of a current flowing through the sensing diode Q1 (Tr34). A total of currents flowing through the differential pair transistors Tr31 and Tr32 is regulated to a substantially constant value by the current mirror circuit. Thus, the start signal output circuit which is small in size, high in sensitivity and low in power consumption can be realized.
摘要翻译：具有输入了特定频率的射频功率（RF）并从其输出直流电位（DC）的RF / DC转换电路的启动信号输出电路包括检测/放大电路210，其包括倍压器波检测器电路10被配置为包括用于感测RF功率的感测二极管Q 1（Tr 34），包括差分对晶体管Tr 31和Tr 32的差分放大器和电流镜电路。差分对晶体管的一个Tr 31的基极电流与流经感测二极管Q 1（Tr 34）的电流的直流分量基本一致。流过差分对晶体管Tr 31和Tr 32的总电流通过电流镜电路被调节到基本恒定的值。因此，可以实现尺寸小，灵敏度高，功耗低的启动信号输出电路。

10. 发明授权

US06495950B1 Deflection yoke for color cathode-ray tube 失效
标题翻译：彩色阴极射线管偏转磁轭
公开(公告)号：US06495950B1
公开(公告)日：2002-12-17
申请号：US09533363
申请日：2000-03-22
申请人： Katsumi Ito , Akihiko Mori , Kazuhiko Endo
发明人： Katsumi Ito , Akihiko Mori , Kazuhiko Endo
IPC分类号： H01J2970
CPC分类号： H01J29/703
摘要： A deflection yoke capable of easily adjusting a member having a pair of magnetic pieces by moving the member to a standard state in the case of correcting misconvergence. According to the deflection yoke of the invention, a member having a pair of magnetic pieces disposed in the horizontal deflection direction is attached to an electron gun side of the deflection yoke. The shape of a part of each of ends of the member coincides with a part of the outer shape of the electron gun side of the deflection yoke. The adjusting person can easily set the member into the standard state by adjusting the parts with his/her fingers. By moving the member in the horizontal direction from such a state, misconvergence can be corrected.
摘要翻译：一种偏转线圈，其能够通过在校正失会聚的情况下将构件移动到标准状态来容易地调节具有一对磁片的构件。根据本发明的偏转线圈，具有沿水平偏转方向设置的一对磁性片的构件安装在偏转线圈的电子枪侧。构件的每个端部的一部分的形状与偏转线圈的电子枪侧的外部形状的一部分重合。调整人员可以通过用手指调节部件，轻松地将会员设置为标准状态。通过从这种状态沿水平方向移动构件，可以纠正失会聚。

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