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1. 发明申请

US20070246804A1 ORGANIC INSULATING FILM, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE USING SUCH ORGANIC INSULATING FILM AND MANUFACTURING METHOD THEREOF 有权
标题翻译：有机绝缘膜，其制造方法，使用这种有机绝缘膜的半导体器件及其制造方法
公开(公告)号：US20070246804A1
公开(公告)日：2007-10-25
申请号：US11534941
申请日：2006-09-25
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
IPC分类号： H01L23/52 , C07F7/04
CPC分类号： H01L21/7681 , C23C16/30 , C23C16/36 , C23C16/401 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3148 , H01L21/31633 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76808 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance. The present invention relates to an organic film made of one of SiOCH, SiCHN and SiCH that is formed using, as a source, a polyorganosilane whose C/Si ratio is at least 5 or greater and molecular weight is 100 or greater, and a semiconductor device wherein such an organic insulating film is used, and more particularly to a semiconductor device having a trench structure.
摘要翻译：目前被广泛研究的SiC和SiCN的介电常数分别为4.5〜5左右，SiOC为2.8〜3.0左右。随着器件尺寸减小引起的互连尺寸和互连间距的进一步小型化，出现了强烈的要求，即应进一步降低介电常数。此外，由于SiOC与SiCN的蚀刻选择比以及SiOC与SiC的蚀刻选择比小，因此如果使用SiCN或SiC作为蚀刻停止膜，则金属配线层的表面在光刻胶去除时可能被氧化，这导致高接触电阻的问题。本发明涉及使用以C / Si比为5以上且分子量为100以上的聚有机硅烷作为源的SiOCH，SiCHN和SiCH之一构成的有机膜，以及半导体使用这种有机绝缘膜的装置，更具体地说涉及具有沟槽结构的半导体器件。

2. 发明授权

US07910474B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07910474B2
公开(公告)日：2011-03-22
申请号：US12098190
申请日：2008-04-04
申请人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
发明人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L23/5222 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents, and, in particular, a low-carbon-concentration film 6a with a small carbon content is set to be a lower layer therein and a high-carbon-concentration film 6b with a large carbon content is set to be an upper layer therein, whereby the effectual prevention against the Cu diffusion, a high etching selection ratio and good adhesiveness to the Cu interconnection can be certainly provided by the presence of the low-carbon-concentration film 6a, while the overall dielectric constant can be well reduced by the presence of the high-carbon-concentration film 6b.
摘要翻译：本发明的目的是提供一种半导体器件，其包括其间的层间绝缘膜的蚀刻选择率高的阻挡膜，对Cu扩散的良好的预防功能，低介电常数和对Cu互连的优异粘合性及其制造方法。设置在互连或通孔插塞及其上覆层间绝缘膜之间的阻挡膜（例如，第二阻挡膜6）具有由多个含有硅和碳的膜（优选硅，碳和氮），具有不同的碳含量，特别是具有小碳含量的低碳浓度膜6a被设定为下层，并且具有大碳含量的高碳浓度膜6b为在其中设置为上层，由此通过低碳浓度膜6a的存在可以确定地提供对Cu扩散的有效防止，高的蚀刻选择率和对Cu互连的良好的粘合性，而整个电介质通过高碳浓度膜6b的存在可以很好地降低常数。

3. 发明授权

US07763979B2 Organic insulating film, manufacturing method thereof, semiconductor device using such organic insulating film and manufacturing method thereof 有权
标题翻译：有机绝缘膜及其制造方法，使用该有机绝缘膜的半导体装置及其制造方法
公开(公告)号：US07763979B2
公开(公告)日：2010-07-27
申请号：US11534941
申请日：2006-09-25
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Kazuhiko Endo
IPC分类号： H01L25/34
CPC分类号： H01L21/7681 , C23C16/30 , C23C16/36 , C23C16/401 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3148 , H01L21/31633 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76808 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced.Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.The present invention relates to an organic film made of one of SiOCH, SiCHN and SiCH that is formed using, as a source, a polyorganosilane whose C/Si ratio is at least 5 or greater and molecular weight is 100 or greater, and a semiconductor device wherein such an organic insulating film is used, and more particularly to a semiconductor device having a trench structure.
摘要翻译：目前被广泛研究的SiC和SiCN的介电常数分别为4.5〜5左右，SiOC为2.8〜3.0左右。随着器件尺寸减小引起的互连尺寸和互连间距的进一步小型化，出现了强烈的要求，即应进一步降低介电常数。此外，由于SiOC与SiCN的蚀刻选择比以及SiOC与SiC的蚀刻选择比小，因此如果使用SiCN或SiC作为蚀刻停止膜，则金属配线层的表面在光刻胶去除时可能被氧化，这导致高接触电阻的问题。本发明涉及使用以C / Si比为5以上且分子量为100以上的聚有机硅烷作为源的SiOCH，SiCHN和SiCH之一构成的有机膜，以及半导体使用这种有机绝缘膜的装置，更具体地说涉及具有沟槽结构的半导体器件。

4. 发明授权

US07391115B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07391115B2
公开(公告)日：2008-06-24
申请号：US10768676
申请日：2004-02-02
申请人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
发明人： Tatsuya Usami , Noboru Morita , Koichi Ohto , Kazuhiko Endo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L23/5222 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents, and, in particular, a low-carbon-concentration film 6a with a small carbon content is set to be a lower layer therein and a high-carbon-concentration film 6b with a large carbon content is set to be an upper layer therein, whereby the effectual prevention against the Cu diffusion, a high etching selection ratio and good adhesiveness to the Cu interconnection can be certainly provided by the presence of the low-carbon-concentration film 6a, while the overall dielectric constant can be well reduced by the presence of the high-carbon-concentration film 6b.
摘要翻译：本发明的目的是提供一种半导体器件，其包括其间的层间绝缘膜的蚀刻选择率高的阻挡膜，对Cu扩散的良好的预防功能，低介电常数和对Cu互连的优异粘合性及其制造方法。设置在互连或通孔插塞及其上覆层间绝缘膜之间的阻挡膜（例如，第二阻挡膜6）具有由多个含有硅和碳的膜（优选硅，碳和氮），具有不同的碳含量，特别是具有小碳含量的低碳浓度膜6a被设定为下层，并且具有大碳的高碳浓度膜6b 含量被设定为上层，由此可以通过低碳浓度膜6a的存在来确定地提供对Cu扩散的有效防止，高的蚀刻选择率和对Cu互连的良好的粘附性，同时通过存在高碳浓度膜6b可以很好地降低总介电常数。

5. 发明授权

US07615498B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07615498B2
公开(公告)日：2009-11-10
申请号：US11655261
申请日：2007-01-19
申请人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
发明人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76832
摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
摘要翻译：半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210，SiO 2膜212和SiCN膜 214。第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。第二SiOC膜210的碳含量被调节为大于第一SiOC膜204的碳含量。这使得可以在保持绝缘夹层的低介电常数的同时，改善绝缘中间层与其它绝缘层的粘附性。

6. 发明申请

US20070045861A1 Semiconductor device, and production method for manufacturing such semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070045861A1
公开(公告)日：2007-03-01
申请号：US11591704
申请日：2006-11-02
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.
摘要翻译：半导体器件具有半导体衬底和设置在其上的多层布线装置。多层绞合装置包括其中形成有金属布线图案的至少一个绝缘层结构。绝缘层结构包括第一SiOCH层，形成在第一SiOCH层上的第二SiOCH层和形成在第二SiOCH层上的二氧化硅（SiO 2）层。第二SiOCH层的碳（C）密度低于第一SiOCH层的碳（C）密度，氢（H）密度低于第一SiOCH层的密度，氧（O）密度高于第一SiOCH层。

7. 发明授权

US07180191B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07180191B2
公开(公告)日：2007-02-20
申请号：US11048929
申请日：2005-02-03
申请人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
发明人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76832
摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
摘要翻译：半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210， SUB>膜212和形成在其上的SiCN膜214。第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。第二SiOC膜210的碳含量被调整为大于第一SiOC膜204的碳含量。这使得可以在保持绝缘中间层的低介电常数的同时提高绝缘中间层与其它绝缘层的粘附性。

8. 发明申请

US20060060975A1 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060060975A1
公开(公告)日：2006-03-23
申请号：US11219784
申请日：2005-09-07
申请人： Tatsuya Usami , Noboru Morita , Koichi Ohto
发明人： Tatsuya Usami , Noboru Morita , Koichi Ohto
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76834 , H01L21/76804 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device comprises a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device comprises an electric conductor, which is provided to extend through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is provided so as to cover side surfaces and a bottom surface of the Cu film 120. This semiconductor device comprises an insulating film 116, which is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).
摘要翻译：提供了一种用于抑制在半导体器件中发生的绝缘击穿的技术。半导体器件包括半导体衬底（未示出），形成在半导体衬底上的层间绝缘膜102和设置在层间绝缘膜102上的多层绝缘膜140。半导体器件包括导电体，其设置成延伸穿过多层绝缘膜140并且包括Cu膜120和阻挡金属膜118。阻挡金属膜118被设置为覆盖Cu膜120的侧表面和底表面。该半导体器件包括设置在多层绝缘膜140和导电体（即Cu膜120和阻挡金属膜118）之间的绝缘膜116。

9. 发明授权

US07563705B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07563705B2
公开(公告)日：2009-07-21
申请号：US11359393
申请日：2006-02-23
申请人： Takashi Tonegawa , Koji Arita , Tatsuya Usami , Noboru Morita , Koichi Ohto , Yoichi Sasaki , Sadayuki Ohnishi , Ryohei Kitao
发明人： Takashi Tonegawa , Koji Arita , Tatsuya Usami , Noboru Morita , Koichi Ohto , Yoichi Sasaki , Sadayuki Ohnishi , Ryohei Kitao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76802 , H01L21/76807 , H01L21/76811 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
摘要翻译：一种半导体器件的制造方法，包括在包括诸如MSQ，SiC和SiCN的有机低电介质膜的绝缘层中形成通孔的步骤，然后通过阻挡金属将布线材料包埋在通孔中。根据该方法，使用能够代替由有机成分构成的基团（甲基）并覆盖暴露的有机物的表面的He / H 2气体，在形成通孔并且在阻挡金属沉积之前进行等离子体处理具有氢的低介电膜（MSQ）或能够分解基团（甲基）而不去除有机低介电分子的He气体。结果，低电介质膜（MSQ）的表面被重新形成为亲水性，因此提高了与阻挡金属的粘合性，从而可以防止隔离金属的分离和划痕的发生。

10. 发明授权

US07074698B2 Method of fabricating semiconductor device using plasma-enhanced CVD 失效
标题翻译：使用等离子体增强CVD制造半导体器件的方法
公开(公告)号：US07074698B2
公开(公告)日：2006-07-11
申请号：US10766921
申请日：2004-01-30
申请人： Noboru Morita , Tatsuya Usami , Koichi Ohto , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
发明人： Noboru Morita , Tatsuya Usami , Koichi Ohto , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
IPC分类号： H01L21/26 , H01L21/42
CPC分类号： H01L21/02126 , C23C16/325 , C23C16/36 , C23C16/401 , C23C16/46 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device using a PECVD method is provided, which improves the adhesion strength of a deposited dielectric layer to an underlying layer and the reliability of the deposited dielectric layer. After placing a substrate in a chamber, a gas having a thermal conductivity of 0.1 W/mK or greater (e.g., H2 or He) is introduced into the chamber, thereby contacting the gas with the substrate for stabilization of a temperature of the substrate. A desired dielectric layer is deposited on or over the substrate in the chamber using a PECVD method after the step of introducing the gas. As the desired dielectric layer, a dielectric layer having a low dielectric constant, such as a SiCH, SiCHN, or SiOCH layer, is preferably used.
摘要翻译：提供了使用PECVD方法制造半导体器件的方法，其提高了沉积的介电层对下层的粘附强度和沉积的介电层的可靠性。在将基板放置在室中之后，将导热率为0.1W / mK以上的气体（例如H 2 H 2或He）引入到室内，从而使气体与基板接触稳定基板的温度。在引入气体的步骤之后，使用PECVD方法将期望的电介质层沉积在室中的衬底上或衬底上。作为所需的介电层，优选使用具有低介电常数的介电层，例如SiCH，SiCHN或SiOCH层。

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