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1. 发明授权

US08507994B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08507994B2
公开(公告)日：2013-08-13
申请号：US13205314
申请日：2011-08-08
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： H01L27/10
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.
摘要翻译：在包括CMOS反相器的存储单元中，由于漏电流引起的栅极布线的限制和由于设计规则的限制而导致的存储单元面积的增加被抑制。在包括第一反相器和第二反相器的存储单元中布置第一布线和第二布线作为第一金属层。第一布线连接在第一反相器中的两个漏极和第二反相器中的第二栅极布线。第二布线与第二反相器中的两个漏极和第一反相器中的第一栅极布线连接。第一布线布置成与第二栅极布线重叠，并且布置第二布线以与第一栅极布线重叠。第二金属层布置在第一金属层上方，第三金属层布置在第二金属层的上方。

2. 发明申请

US20110186935A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110186935A1
公开(公告)日：2011-08-04
申请号：US13016481
申请日：2011-01-28
申请人： Yoshitaka UEDA , Kouichi Yamada , Atsushi Wada , Shigeto Kobayashi
发明人： Yoshitaka UEDA , Kouichi Yamada , Atsushi Wada , Shigeto Kobayashi
IPC分类号： H01L27/105
CPC分类号： H01L27/105
摘要： A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.
摘要翻译： MOS晶体管包括形成为栅格图案的栅极电极，由栅电极围绕的源极区域和漏极区域以及经由源极触点连接到源极区域的源极金属布线和经由漏极连接到漏极区域的漏极金属布线联系人源金属布线和漏极金属布线沿着栅电极的栅格的一个方向设置。源极区域和漏极区域中的每一个是沿着每个金属布线的长度方向具有长边的矩形形状。源极金属布线和漏极金属布线分别在长度方向上以锯齿形形式分别连接到源极触点和漏极触点。

3. 发明申请

US20110156336A1 IMAGE FORMING APPARATUS 有权
标题翻译：图像形成装置
公开(公告)号：US20110156336A1
公开(公告)日：2011-06-30
申请号：US12968696
申请日：2010-12-15
申请人： Jun Agata , Kenji Matsuzaka , Kouichi Yamada , Masatoshi Takiguchi , Ryukichi Inoue , Masahiko Suzumi , Jun Asami , Sho Taguchi
发明人： Jun Agata , Kenji Matsuzaka , Kouichi Yamada , Masatoshi Takiguchi , Ryukichi Inoue , Masahiko Suzumi , Jun Asami , Sho Taguchi
IPC分类号： B65H7/00 , B65H3/06
CPC分类号： B65H5/34 , B65H5/062 , B65H7/00 , B65H85/00 , B65H2301/51256 , B65H2403/42 , B65H2403/722 , B65H2404/6111 , B65H2405/3322 , B65H2513/104 , B65H2513/41 , Y10S271/902 , B65H2220/02 , B65H2220/01
摘要： A reversely-rotatable roller conveys a sheet having an image formed on its one side at a sheet conveying velocity faster than that of a conveying roller by normal rotation and then, the reversely-rotatable roller conveys the sheet to a re-conveying path by reverse rotation. The sheet conveying velocity of the reversely-rotatable roller when the reversely-rotatable roller reversely rotates is made slower than the sheet conveying velocity when the reversely-rotatable roller normally rotates so that the sheet conveying velocity of the re-conveying roller is substantially equal to or slower than the sheet conveying velocity of the conveying roller.
摘要翻译：反向旋转的辊通过正常旋转将具有在其一侧形成的图像的纸张的输送速度快于输送辊的纸张输送速度，然后反向旋转的辊将纸张传送到反向传送路径回转。当反向旋转辊反转时，反向旋转辊的片材输送速度比反转辊正常旋转时的片材输送速度慢，使得再输送辊的片材输送速度基本上等于或比输送辊的片材输送速度慢。

4. 发明授权

US07476945B2 Memory having reduced memory cell size 有权
标题翻译：存储器具有减小的存储单元大小
公开(公告)号：US07476945B2
公开(公告)日：2009-01-13
申请号：US11073897
申请日：2005-03-08
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/11253 , G11C11/15 , G11C17/06 , H01L27/105 , H01L27/112 , H01L27/11213 , H01L27/11293 , H01L27/224 , Y10S257/903 , Y10S257/905 , Y10S257/909 , Y10S257/91
摘要： A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.
摘要翻译：提供了能够减小存储单元大小的存储器。该存储器包括形成在半导体衬底的主表面的存储单元阵列区域上的第一导电型第一杂质区，用作用于存储单元中包含的二极管的第一电极和多个第二导电型第二杂质区，以规定的间隔形成在第一杂质区域的表面上，各自用作二极管的第二电极。

5. 发明授权

US07474570B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07474570B2
公开(公告)日：2009-01-06
申请号：US11247153
申请日：2005-10-12
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： G11C7/00
CPC分类号： G11C11/22 , G11C7/08 , G11C11/4091
摘要： A semiconductor device capable of improving the accuracy determines whether a prescribed input potential is higher or lower than a reference potential. This semiconductor device comprises first capacitance unit and second capacitance unit having different ON- and OFF-state capacitances. The semiconductor device changes the potential of a first electrode of the first capacitance unit and the potential of a first electrode of the second capacitance unit from a first potential to a second potential thereby enlarging the difference between a potential input in a second electrode of the first capacitance unit and a potential input in a second electrode of the second capacitance unit and comparing the potential input in the second electrode of the first capacitance unit and the potential input in the second electrode of the second capacitance unit with each other.
摘要翻译：能够提高精度的半导体装置决定规定的输入电位是高于还是低于参考电位。该半导体器件包括具有不同导通和截止状态电容的第一电容单元和第二电容单元。半导体器件将第一电容单元的第一电极的电位和第二电容单元的第一电极的电位从第一电位改变为第二电位，从而扩大第一电容的第二电极中的电位输入之间的差电容单元和第二电容单元的第二电极中的电位输入，并将第一电容单元的第二电极中的电位输入与第二电容单元的第二电极中的电位输入进行比较。

6. 发明申请

US20070242542A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070242542A1
公开(公告)日：2007-10-18
申请号：US11727687
申请日：2007-03-28
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： G11C7/02
CPC分类号： G11C17/10
摘要： A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.
摘要翻译：获得可高速操作的存储器。该存储器包括多个字线，每个连接到多个字线中的每一个用于通过选择相应的字线来进入导通状态的第一晶体管，多个存储单元包括具有连接到源极或漏极区域的阴极的二极管的第一晶体管的漏极或源极区域连接的数据确定部分，用于确定从所选存储器单元读取的数据。

7. 发明申请

US20070237016A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070237016A1
公开(公告)日：2007-10-11
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及每个连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

8. 发明授权

US07248304B2 Digital broadcast receiving apparatus 有权
标题翻译：数字广播接收装置
公开(公告)号：US07248304B2
公开(公告)日：2007-07-24
申请号：US11337517
申请日：2006-01-24
申请人： Shigeyuki Okada , Kouichi Yamada , Mamoru Mukuno
发明人： Shigeyuki Okada , Kouichi Yamada , Mamoru Mukuno
IPC分类号： H04N5/50
CPC分类号： H04N21/4383 , H04N5/4401 , H04N21/4263 , H04N21/433 , H04N21/4382 , H04N21/44016 , H04N21/44209 , H04N21/4435
摘要： The digital broadcast receiving apparatus according to the present invention includes a tuning unit for outputting normal image data for performing a normal reproduction operation corresponding to a user selected channel, a memory unit for outputting background image data for performing a background reproduction operation when the normal reproduction operation cannot be performed, a data selector for receiving the normal image data and the background image data and outputting one of the normal image data and the background image data, and an MPEG video decode unit for decoding image data output by the data selector to generate an image signal. The tuning unit successively receives the respective channel selected in the background independently of the user selection, and stores the background image data corresponding to the respective channels in the memory unit.
摘要翻译：根据本发明的数字广播接收装置包括：调谐单元，用于输出用于执行与用户选择的频道相对应的正常再现操作的正常图像数据;存储单元，用于输出当正常再现时执行背景再现操作的背景图像数据无法执行操作的数据选择器，用于接收正常图像数据和背景图像数据并输出正常图像数据和背景图像数据之一的数据选择器，以及用于解码由数据选择器输出的图像数据的MPEG视频解码单元，以产生图像信号。调谐单元连续地接收与用户选择无关地在背景中选择的相应频道，并且将与各个频道相对应的背景图像数据存储在存储单元中。

9. 发明申请

US20070019459A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070019459A1
公开(公告)日：2007-01-25
申请号：US11489535
申请日：2006-07-20
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： G11C17/00
CPC分类号： G11C17/06 , H01L27/112 , H01L27/11253
摘要： A memory capable of reducing the memory cell size is provided. This memory comprises a plurality of memory cells including diodes, a plurality of bit lines and an n-type impurity region arranged to intersect with the bit lines for functioning as cathodes of the diodes included in the memory cells and a word line. The n-type impurity region is divided every bit line group formed by a prescribed number of bit lines.
摘要翻译：提供了能够减小存储单元大小的存储器。该存储器包括多个存储单元，包括二极管，多个位线和n位杂质区域，其布置成与位线相交，用作存储单元中包含的二极管的阴极和字线。将n型杂质区域划分为由规定数量的位线形成的每个位线组。

10. 发明授权

US5477610A Method of manufacturing composite conductor having heat resistance or oxidation resistance 失效
标题翻译：具有耐热性或抗氧化性的复合导体的制造方法
公开(公告)号：US5477610A
公开(公告)日：1995-12-26
申请号：US210624
申请日：1994-03-18
申请人： Kazuo Sawada , Shinji Inazawa , Kouichi Yamada
发明人： Kazuo Sawada , Shinji Inazawa , Kouichi Yamada
IPC分类号： H01B5/02 , H01B1/02 , H01B3/10 , H01B7/28 , H01B7/29 , H01B13/00 , H01B13/14 , H01B13/20
CPC分类号： H01B3/105 , H01B1/026 , H01B13/14 , H01B7/2806 , H01B7/292 , Y10T29/49123 , Y10T428/12576 , Y10T428/292 , Y10T428/2938 , Y10T428/294 , Y10T428/2949 , Y10T428/2958
摘要： A method is provided for manufacturing a composite conductor having a copper or copper alloy core, a conductive ceramic intermediate layer and a nickel outer layer, and being suitable for high temperature applications. The method involves first preparing the copper or copper alloy core, then extruding a mixture of conductive ceramic power and a binder around the core to form the ceramic layer, and then applying a nickel tape as an outer covering. As further steps, a seam of the nickel tape covering is welded, the product is passed through a cladding die, and finally the product is drawn to form the desired conductor with a preselected diameter. Optionally, a further ceramic layer can be applied around the nickel layer.
摘要翻译：提供了一种用于制造具有铜或铜合金芯，导电陶瓷中间层和镍外层的复合导体的方法，并且适用于高温应用。该方法包括首先制备铜或铜合金芯，然后在芯周围挤出导电陶瓷功率和粘合剂的混合物以形成陶瓷层，然后施加镍带作为外覆层。作为进一步的步骤，镍带覆盖层的接缝被焊接，产品通过包层模头，最后拉制产品以形成预定直径的所需导体。任选地，可以在镍层周围施加另外的陶瓷层。

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