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1. 发明授权

US07724833B2 Receiver for an LDPC based TDS-OFDM communication system 失效
标题翻译：用于基于LDPC的TDS-OFDM通信系统的接收机
公开(公告)号：US07724833B2
公开(公告)日：2010-05-25
申请号：US11740712
申请日：2007-04-26
申请人： Lin Yang , Dinesh Venkatachalam
发明人： Lin Yang , Dinesh Venkatachalam
IPC分类号： H04L27/28
CPC分类号： H04L27/2647 , H04L1/0045 , H04L1/0057 , H04L25/0202 , H04L27/2656 , H04L2025/03414
摘要： An LDPC based TDS-OFDM receiver for demodulating an LDPC encoded TDS-OFDM modulated RF signal downconverted to an IF signal includes a synchronization block, an equalization block, an OFDM demodulation block and a FEC decoder block. The synchronization block generates a baseband signal from a digitized IF signal and performs correlation of a PN sequence in a signal frame of the received RF signal with a corresponding locally generated PN sequence to provide signals for performing carrier recovery, timing recovery and parameters for channel estimation. The equalization block performs channel estimation and channel equalization. The OFDM demodulation block performs demodulation on the baseband signal to recover OFDM symbols and converts the OFDM symbols to frequency domain. The FEC decoder block includes an LDPC decoder for decoding the OFDM symbols based on the LDPC code to generate a digital output signal indicative of the data content of the RF signal.
摘要翻译：用于解调下变频到IF信号的LDPC编码的TDS-OFDM调制RF信号的基于LDPC的TDS-OFDM接收机包括同步块，均衡块，OFDM解调块和FEC解码器块。同步块从数字化IF信号产生基带信号，并且执行接收的RF信号的信号帧中的PN序列与相应的本地生成的PN序列的相关性，以提供用于执行载波恢复，定时恢复和用于信道估计的参数的信号。均衡块执行信道估计和信道均衡。 OFDM解调块对基带信号进行解调以恢复OFDM符号，并将OFDM符号转换为频域。 FEC解码器块包括LDPC解码器，用于基于LDPC码解码OFDM符号，以产生指示RF信号的数据内容的数字输出信号。

2. 发明申请

US20080025419A1 UNIFIED RECEIVER STRUCTURE FOR TDS-OFDM SIGNALS AND TDS SINGLE CARRIER SIGNALS 审中-公开
标题翻译：用于TDS-OFDM信号和TDS单载波信号的统一接收机结构
公开(公告)号：US20080025419A1
公开(公告)日：2008-01-31
申请号：US11550377
申请日：2006-10-17
申请人： Lin Yang , Dinesh Venkatachalam
发明人： Lin Yang , Dinesh Venkatachalam
IPC分类号： H04K1/10
CPC分类号： H04L27/0008 , H04L25/0202 , H04L27/2647 , H04L27/2656 , H04L2025/03414
摘要： A receiver adapted to receive both OFDM signals and single carrier signals is provided. The receiver possesses substantially commonly shared circuitry or function blocks, except an IFT (inverse Fourier transform) block adapted a receive frequency domain signals from a channel equalizer for converting the received frequency domain signal to a time domain signal, and a bypass for bypassing the IFT.
摘要翻译：提供了适于接收OFDM信号和单载波信号的接收机。接收机具有基本上共同的共享电路或功能块，除了适用于来自信道均衡器的接收频域信号的IFT（逆傅里叶变换）块，用于将接收到的频域信号转换为时域信号，旁路用于绕过IFT 。

3. 发明申请

US20080025424A1 Receiver For An LDPC based TDS-OFDM Communication System 失效
标题翻译：用于基于LDPC的TDS-OFDM通信系统的接收机
公开(公告)号：US20080025424A1
公开(公告)日：2008-01-31
申请号：US11740712
申请日：2007-04-26
申请人： Lin Yang , Dinesh Venkatachalam
发明人： Lin Yang , Dinesh Venkatachalam
IPC分类号： H04B1/69
CPC分类号： H04L27/2647 , H04L1/0045 , H04L1/0057 , H04L25/0202 , H04L27/2656 , H04L2025/03414
摘要： An LDPC based TDS-OFDM receiver for demodulating an LDPC encoded TDS-OFDM modulated RF signal downconverted to an IF signal includes a synchronization block, an equalization block, an OFDM demodulation block and a FEC decoder block. The synchronization block generates a baseband signal from a digitized IF signal and performs correlation of a PN sequence in a signal frame of the received RF signal with a corresponding locally generated PN sequence to provide signals for performing carrier recovery, timing recovery and parameters for channel estimation. The equalization block performs channel estimation and channel equalization. The OFDM demodulation block performs demodulation on the baseband signal to recover OFDM symbols and converts the OFDM symbols to frequency domain. The FEC decoder block includes an LDPC decoder for decoding the OFDM symbols based on the LDPC code to generate a digital output signal indicative of the data content of the RF signal.
摘要翻译：用于解调下变频到IF信号的LDPC编码的TDS-OFDM调制RF信号的基于LDPC的TDS-OFDM接收机包括同步块，均衡块，OFDM解调块和FEC解码器块。同步块从数字化IF信号产生基带信号，并且执行接收的RF信号的信号帧中的PN序列与相应的本地生成的PN序列的相关性，以提供用于执行载波恢复，定时恢复和用于信道估计的参数的信号。均衡块执行信道估计和信道均衡。 OFDM解调块对基带信号进行解调以恢复OFDM符号，并将OFDM符号转换为频域。 FEC解码器块包括LDPC解码器，用于基于LDPC码解码OFDM符号，以产生指示RF信号的数据内容的数字输出信号。

4. 发明授权

US06449274B1 Apparatus for high speed communication system 有权
标题翻译：高速通讯系统装置
公开(公告)号：US06449274B1
公开(公告)日：2002-09-10
申请号：US09699261
申请日：2000-10-27
申请人： Brian D. Holden , Brian D. Alleyne , Darren S. Braun , Imran Chaudhri , Kevin Reno , Nadeem Haq , Chee Hu , Raghavan P Menon , Steve T Sprouse , Dinesh Venkatachalam
发明人： Brian D. Holden , Brian D. Alleyne , Darren S. Braun , Imran Chaudhri , Kevin Reno , Nadeem Haq , Chee Hu , Raghavan P Menon , Steve T Sprouse , Dinesh Venkatachalam
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04J2203/0071 , H04L49/1576 , H04L49/203 , H04L49/256 , H04L49/309 , H04L2012/5635 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679 , H04L2012/5681
摘要： Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
摘要翻译：在高速可伸缩交换系统中有用的方法和设备包括每个虚拟通道排队的无记忆交换结构，数字相位对准器，随机和补码连接模式，中点负确认和输出否定确认方案等。一部分描述了路由表和交换元件的特定实施例以说明本发明的各种技术和设备。

5. 发明申请

US20080028282A1 RECEIVER ARCHITECTURE HAVING A LDPC DECODER WITH AN IMPROVED LLR UPDATE METHOD FOR MEMORY REDUCTION 审中-公开
标题翻译：具有用于减少存储器的改进的LLR更新方法的LDPC解码器的接收机架构
公开(公告)号：US20080028282A1
公开(公告)日：2008-01-31
申请号：US11557491
申请日：2006-11-07
申请人： Yan Zhong , Abhiram Prabhakar , Dinesh Venkatachalam
发明人： Yan Zhong , Abhiram Prabhakar , Dinesh Venkatachalam
IPC分类号： H03M13/03
CPC分类号： H03M13/116 , H03M13/1102 , H03M13/1114 , H03M13/1117 , H03M13/1122 , H03M13/114 , H03M13/152 , H03M13/251 , H03M13/2732 , H03M13/2906 , H03M13/6505
摘要： The present invention provides a reduced memory implementation for the min-sum algorithm compared to traditional hardware implementations. The improvement includes innovative MIN_SUM method with reduced memory requirements suitable of computer implementation that combines the traditional row update process and column update process into a single process, in that the traditional CNU unit and VNU unit are combined into a single CVNU unit. The improvement not only reduces the time required for decoding by half, but also reduces the logic and routing efforts. Furthermore, instead of storing the whole intermediate LLR values using a significant number of memories, only a set of parameters associated with the intermediate LLR values is stored. The set of parameters includes: 1. sign of LLR; 2. the minimum LLR, 3. sub-minimum LLR, and 4. the column location of minimum value in each row. Therefore, as compared with the traditional LDPC decoder implementation, the required memory size of the present invention is significantly or tremendously reduced.
摘要翻译：与传统硬件实现相比，本发明提供了用于最小和算法的减少的存储器实现。该改进包括创新的MIN_SUM方法，具有较少的内存要求，适合计算机实现，将传统的行更新过程和列更新过程组合到一个过程中，传统的CNU单元和VNU单元组合成一个CVNU单元。该改进不仅将解码所需的时间缩短了一半，而且减少了逻辑和布线工作。此外，代替使用大量存储器存储整个中间LLR值，仅存储与中间LLR值相关联的一组参数。参数集包括：1. LLR的符号; 2.最小LLR，3. sub-minimum LLR和4.每行最小值的列位置。因此，与传统的LDPC解码器实现相比，本发明所需的存储器大小显着或大大降低。

6. 发明申请

US20080025377A1 METHOD AND DEVICE FOR FREQUENCY DOMAIN COMPENSATION FOR CHANNEL ESTIMATION AT AN OVER SAMPLING RATE IN A TDS_OFDM RECEIVER 审中-公开
标题翻译：用于在TDS_OFDM接收器中采样速率进行频域估计的频域补偿的方法和设备
公开(公告)号：US20080025377A1
公开(公告)日：2008-01-31
申请号：US11550316
申请日：2006-10-17
申请人： QIN LIU , Dinesh Venkatachalam
发明人： QIN LIU , Dinesh Venkatachalam
IPC分类号： H04B1/00
CPC分类号： H04L25/0234 , H04L27/2647 , H04L27/2656 , H04L2025/03414
摘要： In a TDS-OFDM receiver a device for frequency-domain compensation for channel estimation at an over-sampling rate is provided. The device includes a correlater for correlating a first signal and a second signal; a transformer for transforming the correlated signals into a frequency domain; and an interpolater and truncater block for interpolating and truncating the transformed signal to have the interpolated and truncated, transformed signal as a reference for future use.
摘要翻译：在TDS-OFDM接收机中，提供用于以过采样速率进行信道估计的频域补偿的装置。该装置包括用于使第一信号和第二信号相关的相关器; 用于将相关信号变换成频域的变压器; 以及用于内插和截断经变换的信号以使内插和截断的变换信号作为将来使用的参考的内插器和截取器块。

7. 发明授权

US06993020B2 Distributed switch memory architecture 失效
公开(公告)号：US06993020B2
公开(公告)日：2006-01-31
申请号：US10704510
申请日：2003-11-06
申请人： Visveswar Akella , Sanjay Sharma , Amalkiran Bommireddy , Dinesh Venkatachalam
发明人： Visveswar Akella , Sanjay Sharma , Amalkiran Bommireddy , Dinesh Venkatachalam
IPC分类号： H04L12/50
CPC分类号： H04L49/9021 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3036 , H04L49/3072 , H04L49/351 , H04L49/90
摘要： A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.

8. 发明授权

US06697362B1 Distributed switch memory architecture 有权
标题翻译：分布式交换机内存架构
公开(公告)号：US06697362B1
公开(公告)日：2004-02-24
申请号：US09187760
申请日：1998-11-06
申请人： Visveswar Akella , Sanjay Sharma , Amalkiran Bommireddy , Dinesh Venkatachalam
发明人： Visveswar Akella , Sanjay Sharma , Amalkiran Bommireddy , Dinesh Venkatachalam
IPC分类号： H04J116
CPC分类号： H04L49/9021 , H04L49/101 , H04L49/15 , H04L49/30 , H04L49/3036 , H04L49/3072 , H04L49/351 , H04L49/90
摘要： A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.
摘要翻译：一种用于将数据包从源端口传输到目的端口的分布式存储器切换系统，包括：多个端口，包括源端口和目的端口，其中分组从源端口发送到目的端口; 内存池以及耦合在所述多个端口和所述存储器池之间的互连级，使得所述互连级允许分组经由所述存储器池从所述源端口传送到所述目的地端口。

9. 发明授权

US07535898B2 Distributed switch memory architecture 有权
标题翻译：分布式交换机内存架构
公开(公告)号：US07535898B2
公开(公告)日：2009-05-19
申请号：US11315565
申请日：2005-12-22
申请人： Visveswar Akella , Sanjay Sharma , Amalkiran Bommireddy , Dinesh Venkatachalam
发明人： Visveswar Akella , Sanjay Sharma , Amalkiran Bommireddy , Dinesh Venkatachalam
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3072
摘要： A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.
摘要翻译：一种用于将数据包从源端口传输到目的端口的分布式存储器切换系统，包括：多个端口，包括源端口和目的端口，其中分组从源端口发送到目的端口; 内存池以及耦合在所述多个端口和所述存储器池之间的互连级，使得所述互连级允许分组经由所述存储器池从所述源端口传送到所述目的地端口。

10. 发明申请

US20080186217A1 LOW PIN COUNT HIGH SPEED INTERFACE FOR VIDEO AND AUDIO CODEC APPLICATIONS 审中-公开
标题翻译：用于视频和音频编解码应用的低引脚计数高速接口
公开(公告)号：US20080186217A1
公开(公告)日：2008-08-07
申请号：US11672036
申请日：2007-02-06
申请人： Lei Chen , Dinesh Venkatachalam
发明人： Lei Chen , Dinesh Venkatachalam
IPC分类号： H03M3/04
CPC分类号： H04B14/06 , H04B1/40
摘要： A receiver is provided that comprises at least one tuner. The tuner comprises a housing or packaging wall inclosing at least some elements of the tuner. The tuner further comprises at least one pin or lead leading outside or away from the housing, and a sigma-delta modulator receiving an analog input stream having at least one frequency from at least one tuner and output at least 1-bit data stream, with each 1-bit data stream associated with a physical communications line terminating on the lead or pin. The receiver has at least one digital filter digitally coupled to the sigma-delta modulator for filtering the at least 1-bit data stream.
摘要翻译：提供了包括至少一个调谐器的接收器。调谐器包括封闭调谐器的至少一些元件的壳体或包装壁。该调谐器还包括至少一个引导到外部或远离壳体的引脚或引线，以及Σ-Δ调制器，接收来自至少一个调谐器的至少一个频率的模拟输入流，并输出至少1位数据流，与物理通信线路相关联的每个1比特数据流终止于引线或引脚。接收器具有数字耦合到Σ-Δ调制器的至少一个数字滤波器，用于对至少1位数据流进行滤波。

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