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1. 发明授权

US08023345B2 Iteratively writing contents to memory locations using a statistical model 有权
标题翻译：使用统计模型迭代地将内容写入内存位置
公开(公告)号：US08023345B2
公开(公告)日：2011-09-20
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

2. 发明授权

US08897062B2 Memory programming for a phase change memory cell 有权
标题翻译：相变存储单元的存储器编程
公开(公告)号：US08897062B2
公开(公告)日：2014-11-25
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00 , G11C13/00 , G11C29/02
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

3. 发明申请

US20110228600A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20110228600A1
公开(公告)日：2011-09-22
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/21
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

4. 发明申请

US20100214829A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

5. 发明授权

US08166368B2 Writing a special symbol to a memory to indicate the absence of a data signal 有权
标题翻译：向存储器写入一个特殊的符号来表示没有数据信号
公开(公告)号：US08166368B2
公开(公告)日：2012-04-24
申请号：US12391678
申请日：2009-02-24
申请人： Luis A. Lastras-Montano , John P. Karidis , Stefanie R. Chiras , Mayank Sharma , Thomas Mittelholzer , Michele M. Franceschini
发明人： Luis A. Lastras-Montano , John P. Karidis , Stefanie R. Chiras , Mayank Sharma , Thomas Mittelholzer , Michele M. Franceschini
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , H03M13/15 , H03M13/1515 , H03M13/154
摘要： A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.
摘要翻译：一种用于在存储器系统中写入的方法，包括接收与存储器中的存储器位置相对应的地址，接收要写入的期望内容，将期望内容编码为符号，以及使用迭代写入将符号写入存储器位置处理至少一次写入和一次读取到存储器位置。迭代写入过程包括确定符号是否成功写入存储器位置，并响应于被成功写入存储器位置的符号退出迭代写入过程。迭代写入过程还包括如果已经满足停止条件，则确定是否满足了停止条件并退出迭代写入过程。一旦迭代写入过程已被退出，存储器位置可以被识别为用特殊符号写入的候选。

6. 发明申请

US20100218071A1 WRITING A SPECIAL SYMBOL TO A MEMORY TO INDICATE THE ABSENCE OF A DATA SIGNAL 有权
标题翻译：向存储器写入特殊符号，以显示数据信号的无效
公开(公告)号：US20100218071A1
公开(公告)日：2010-08-26
申请号：US12391678
申请日：2009-02-24
申请人： Luis A. Lastras-Montano , John P. Karidis , Stefanie R. Chiras , Mayank Sharma , Thomas Mittelholzer , Michele M. Franceschini
发明人： Luis A. Lastras-Montano , John P. Karidis , Stefanie R. Chiras , Mayank Sharma , Thomas Mittelholzer , Michele M. Franceschini
IPC分类号： G06F12/00 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , H03M13/15 , H03M13/1515 , H03M13/154
摘要： A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.
摘要翻译：一种用于在存储器系统中写入的方法，包括接收与存储器中的存储器位置相对应的地址，接收要写入的期望内容，将期望内容编码为符号，以及使用迭代写入将符号写入存储器位置处理至少一次写入和一次读取到存储器位置。迭代写入过程包括确定符号是否成功写入存储器位置，并响应于被成功写入存储器位置的符号退出迭代写入过程。迭代写入过程还包括如果已经满足停止条件，则确定是否满足了停止条件并退出迭代写入过程。一旦迭代写入过程已被退出，存储器位置可以被识别为用特殊符号写入的候选。

7. 发明申请

US20110252215A1 COMPUTER MEMORY WITH DYNAMIC CELL DENSITY 审中-公开
标题翻译：具有动态细胞密度的计算机存储器
公开(公告)号：US20110252215A1
公开(公告)日：2011-10-13
申请号：US12757738
申请日：2010-04-09
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin Qureshi
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin Qureshi
IPC分类号： G06F12/02
CPC分类号： G11C11/5628 , G06F12/0238 , G11C11/5678 , G11C13/0004 , G11C2211/5641 , Y02D10/13
摘要： A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region.
摘要翻译：一种具有动态单元密度的计算机存储器，包括获得第一存储器区域的目标尺寸的方法。第一存储器区域包括以第一密度操作的第一存储器单元。第一存储器单元包括在存储器系统的存储器中。存储器可在第一密度和第二密度下操作。所述方法还包括：确定所述第一存储器区域的当前大小不在所述目标大小的阈值内，并且所述第一存储器区域小于所述目标大小; 识别当前在第二存储器区域以第二密度操作的第二存储器单元，所述第二存储器单元包括在存储器中; 以及在正常系统操作期间将所述第二存储器单元动态地重新分配到所述第一存储器区域中，所述第二存储器单元在被重新分配给所述第一存储器区域之后以所述第一密度操作。

8. 发明授权

US08341501B2 Adaptive endurance coding of non-volatile memories 有权
标题翻译：非易失性存储器的适应性耐力编码
公开(公告)号：US08341501B2
公开(公告)日：2012-12-25
申请号：US12433669
申请日：2009-04-30
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

9. 发明申请

US20120311262A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 审中-公开
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20120311262A1
公开(公告)日：2012-12-06
申请号：US13151043
申请日：2011-06-01
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.
摘要翻译：用于改进性能的存储单元预置，包括包括存储器，高速缓存和存储器控制器的系统。存储器包括由存储单元组成的存储器线。缓存包括对应于存储器线的子集的高速缓存行。存储器控制器与存储器和缓存器通信。存储器控制器被配置为执行一种方法，该方法包括根据达到肮脏状态的高速缓存线来调度将存储器线的存储单元设置为公共指定状态的请求。

10. 发明申请

US20100281340A1 ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的自适应耐久编码
公开(公告)号：US20100281340A1
公开(公告)日：2010-11-04
申请号：US12433669
申请日：2009-04-30
申请人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10 , G06F17/30
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

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