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1. 发明授权

US06769083B1 Test pattern generator, a testing device, and a method of generating a plurality of test patterns 有权
标题翻译：测试模式发生器，测试装置以及产生多个测试模式的方法
公开(公告)号：US06769083B1
公开(公告)日：2004-07-27
申请号：US09437249
申请日：1999-11-10
申请人： Masaru Tsuto , Tatsuya Yamada
发明人： Masaru Tsuto , Tatsuya Yamada
IPC分类号： G06F1100
CPC分类号： G01R31/31921
摘要： A test pattern generator for generating a test pattern for testing electrical characteristics of an electrical device. The test pattern generator comprises a pattern memory (32), a pattern cache memory (54, 180 and 182), a vector memory (12), a read out controller (14 and 170), and a transfer controller (34 and 178). The pattern memory (32) stores the test pattern. The pattern cache memory (54, 180 and 182) stores the test pattern read out from the pattern memory (32). The vector memory (12) stores a vector instruction indicating an order of the test pattern to be generated. The read out controller (14 and 170) judges whether an address of the test pattern to be read out from the pattern memory (32) is to be jumped or not based on the vector instruction read out from the vector memory (12). The transfer controller (34 and 178) reads out the test pattern from the jumped address, and for transferring the jumped address to a pattern cache memory (54, 180 and 182) when the read out controller (14 and 170) judges the address is to be jumped.
摘要翻译：一种用于产生用于测试电气设备的电特性的测试图案的测试图案发生器。测试图案生成器包括图形存储器（32），图案高速缓冲存储器（54,180和182），向量存储器（12），读出控制器（14和170）以及传送控制器（34和178）。图案存储器（32）存储测试图案。图案高速缓冲存储器（54,180和182）存储从图案存储器（32）读出的测试图案。矢量存储器（12）存储指示要生成的测试图案的顺序的矢量指令。读出控制器（14和170）基于从向量存储器（12）读出的向量指令来判断是否要跳过要从模式存储器（32）读出的测试图案的地址。传输控制器（34和178）从跳转的地址读出测试模式，并且当读出的控制器（14和170）判断地址是，将跳转的地址传送到模式高速缓冲存储器（54,180和182）要跳了

2. 发明授权

US08692566B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08692566B2
公开(公告)日：2014-04-08
申请号：US13118585
申请日：2011-05-31
申请人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： G01R31/00
CPC分类号： G06F11/2733 , G01R31/2834 , G01R31/31907 , H04L43/50
摘要： Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.
摘要翻译：提供了一种测试装置，包括多个测试部分和同步部分，其同步多个测试部分中的至少两个测试部分的操作。当在相应的程序的执行期间满足预定条件并且测试部分进入同步待机状态时，每个测试部分向同步部分发送同步待机命令，并且在从所有一个接收到同步待命命令的条件下，多个测试部中的多个预定测试部分，同步部分同步地将多个测试部分中的两个或更多个预定测试部分同步地提供结束同步待机状态的同步信号。

3. 发明申请

US20100142392A1 TEST APPARATUS AND TEST METHOD 有权
标题翻译：测试装置和测试方法
公开(公告)号：US20100142392A1
公开(公告)日：2010-06-10
申请号：US12569796
申请日：2009-09-29
申请人： Shinichi ISHIKAWA , Masaru GOISHI , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi ISHIKAWA , Masaru GOISHI , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： H04L12/26
CPC分类号： H04L43/50
摘要： There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.
摘要翻译：提供了一种用于测试至少一个被测设备的测试装置，包括存储多个分组列表的分组列表存储部分，每个分组列表包括在测试设备和被测试的至少一个设备之间传送的一系列分组，根据被设计为测试被测试的至少一个设备的测试程序的执行流程来指定执行多个分组列表的顺序的流程控制部分，以及顺序地传送一系列分组的分组通信部分包括在由测试装置和被测试的至少一个设备之间由流量控制部分顺序指定的分组列表中，以测试被测试的至少一个设备。

4. 发明授权

US06601204B1 Pattern generating method, pattern generator using the method, and memory tester using the pattern generator 失效
标题翻译：图案生成方法，使用该方法的图案生成器，以及使用图案生成器的存储器测试器
公开(公告)号：US06601204B1
公开(公告)日：2003-07-29
申请号：US09717715
申请日：2000-11-21
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： G01R3128
CPC分类号： G11C29/56 , G11C29/02
摘要： After initializing a Direct Rambus DRAM under test with initialization data, an address, pattern data and mask data are provided to the memory to effect therein a byte-wise masked write of the pattern data, and parallel mask data is converted to plural pieces of serial mask data in accordance with burst addresses generated in a burst address generating means. Based on the bit logical value of each serial mask data, it is decided whether data of each byte is write-enabled or not in the byte-wise masked write, based on the bit logical value of each serial mask data and either one of the initialization data and the byte-wise masked written pattern data is selected to generate expectation data.
摘要翻译：在初始化用初始化数据测试的直接Rambus DRAM之后，将地址，模式数据和掩模数据提供给存储器，以在其中进行字节屏蔽的模式数据写入，并且并行掩模数据被转换成多个串行根据在脉冲串地址产生装置中产生的脉冲串地址的掩码数据。基于每个串行掩码数据的位逻辑值，基于每个串行掩码数据的位逻辑值，确定每个字节的数据是否在字节屏蔽写入中被写使能，选择初始化数据和字节屏蔽的写入模式数据以产生期望数据。

5. 发明授权

US08165027B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08165027B2
公开(公告)日：2012-04-24
申请号：US12569796
申请日：2009-09-29
申请人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： H04J1/16
CPC分类号： H04L43/50
摘要： There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.
摘要翻译：提供了一种用于测试至少一个被测设备的测试装置，包括存储多个分组列表的分组列表存储部分，每个分组列表包括在测试设备和被测试的至少一个设备之间传送的一系列分组，根据被设计为测试被测试的至少一个设备的测试程序的执行流程来指定执行多个分组列表的顺序的流程控制部分，以及顺序地传送一系列分组的分组通信部分包括在由测试装置和被测试的至少一个设备之间由流量控制部分顺序指定的分组列表中，以测试被测试的至少一个设备。

6. 发明授权

US08149721B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08149721B2
公开(公告)日：2012-04-03
申请号：US12569776
申请日：2009-09-29
申请人： Shinichi Ishikawa , Hajime Sugimura , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Hajime Sugimura , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： H04J1/16
CPC分类号： H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.
摘要翻译：提供了一种用于测试被测设备的测试装置，包括：获取部分，用于从用于模拟被测设备的操作的仿真环境中获取在测试设备和被测设备之间传送的分组序列;分组通信程序生成部，其从所述分组序列生成用于测试的分组通信程序，其中，所述分组通信程序将由所述测试装置执行以将所述分组序列中包括的分组传送到所述测试装置和所述被测试设备之间;以及测试部分执行分组通信程序以通过在测试设备和被测设备之间传送分组来测试待测设备。

7. 发明授权

US6138259A Semiconductor memory testing apparatus 失效
标题翻译：半导体存储器测试仪器
公开(公告)号：US6138259A
公开(公告)日：2000-10-24
申请号：US953518
申请日：1997-10-17
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319 , G11C29/10 , G11C29/56
CPC分类号： G11C29/56 , G01R31/31919
摘要： In a semiconductor memory testing apparatus for testing a DRAM which requires a refresh operation, plural pattern generation parts are operated normally to generate high-speed pattern signals. The plural pattern generation parts are connected to a common sequence control part and controlled by the count value of the same program counter so that they branch to the refresh mode, operate in the refresh mode a plurality of number of times, then return to the main routine and resume the generation of pattern data.
摘要翻译：在用于测试需要刷新操作的DRAM的半导体存储器测试装置中，正常地操作多个模式生成部分以产生高速模式信号。多个图形生成部分连接到公共序列控制部分并由相同的程序计数器的计数值控制，使得它们分支到刷新模式，在刷新模式下多次操作，然后返回到主并且继续生成模式数据。

8. 发明授权

US5850402A Test pattern generator 失效
标题翻译：测试模式发生器
公开(公告)号：US5850402A
公开(公告)日：1998-12-15
申请号：US849653
申请日：1997-09-08
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： G01R31/3181 , G01R31/319 , G01R31/3193 , G11C29/56 , G11C29/00 , G01R31/28
CPC分类号： G01R31/31928 , G01R31/31813 , G01R31/3193 , G11C29/56 , G01R31/31919
摘要： It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.
摘要翻译： PCT No.PCT / JP96 / 00037 Sec。 371日期：1997年9月8日 102（e）日期1997年9月8日PCT提交1996年12月10日PCT公布。公开号WO97 / 25719 日期1997年7月17日当测试具有每位写入使能/禁止控制功能的存储器件时，它将提供一种能够容易地产生任意初始值的期望值数据的测试图形发生器。模式发生器包括响应于来自指令存储器（112）的指令产生控制信号的异或控制器（131），在其一个端子处接收异或控制器（131）的输出信号的与门和反相输出在其另一输入端的数据发生器B（15）的信号和在其一个输入端接收与门（123）的输出的异或门（121），以及数据发生器A（14）的输出端另一个输入端。

9. 发明授权

US09262376B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US09262376B2
公开(公告)日：2016-02-16
申请号：US13734211
申请日：2013-01-04
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： H04B3/46 , G06F17/00 , G01R31/319 , G01R31/26 , G01R31/317
CPC分类号： G06F17/00 , G01R31/2601 , G01R31/31726 , G01R31/31908
摘要： A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.
摘要翻译：同步模式生成单元生成已经内置于DUT中的时钟恢复单元所需的同步模式，以保持与外部电路的链接。门信号产生单元产生门限信号，该信号在向DUT提供矢量模式的周期内被断言。在第一模式中，模式选择单元被配置为使得在门信号被断言的时段期间输出矢量模式，并且在门信号被否定的时段期间输出固定的输出电平。在第二模式中，模式选择单元被配置为使得在门信号被断言的时段期间输出矢量模式，并且在门信号被否定的时段期间输出该同步模式。

10. 发明授权

US08483073B2 Test apparatus and test method 失效
标题翻译：试验装置及试验方法
公开(公告)号：US08483073B2
公开(公告)日：2013-07-09
申请号：US12569806
申请日：2009-09-29
申请人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： G01R31/08
CPC分类号： H04L49/90 , H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.
摘要翻译：提供了一种用于测试被测设备的测试设备，包括接收来自被测设备的分组的接收部分，分组数据序列存储部分，其存储包括在每种类型的分组中的数据序列和接收的数据由接收部分接收的分组，发送数据处理部分，其从分组数据序列存储部分读取数据，并通过调整要发送到被测设备的数据包的数据序列的预定部分来生成测试数据序列，以具有与接收到的数据相对应的值，以及发送部，其将由发送数据处理部生成的测试数据序列发送给被测设备。

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