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1. 发明授权

US08269515B2 High impedance, high parallelism, high temperature memory test system architecture 有权
标题翻译：高阻抗，高并行度，高温记忆测试系统架构
公开(公告)号：US08269515B2
公开(公告)日：2012-09-18
申请号：US12849700
申请日：2010-08-03
申请人： Romi O. Mayder
发明人： Romi O. Mayder
IPC分类号： G01R31/20
CPC分类号： G01R31/31924 , G01R31/31928
摘要： An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head.
摘要翻译：在自动测试设备中与探头一起使用的电子设备包括第一和第二多个半导体器件。第一多个半导体器件被布置成形成布置成耦合到被测器件的至少一个驱动器。所述至少一个驱动器被配置为将信号发送到所述至少一个被测器件。第二多个半导体器件被布置成形成布置成耦合到被测器件的至少一个接收器。所述至少一个接收器被配置为从所述至少一个被测器件接收信号。第二多个半导体器件中的每一个具有小于约300μm的厚度，不包括任何电互连。所述至少一个接收器适于直接安装到探针头。

2. 发明授权

US08239147B2 Test apparatus and manufacturing method 失效
标题翻译：试验装置及制造方法
公开(公告)号：US08239147B2
公开(公告)日：2012-08-07
申请号：US12388521
申请日：2009-02-19
申请人： Daisuke Watanabe , Toshiyuki Okayasu
发明人： Daisuke Watanabe , Toshiyuki Okayasu
IPC分类号： G01R31/00 , G01R21/00
CPC分类号： G01R31/31922 , G01R31/31924 , G01R31/31928 , H04B17/0085 , H04B17/21 , H04L25/03114 , H04L25/03343 , Y10T29/49004
摘要： Provided is a test apparatus that tests a device under test, comprising a test signal generating section that generates a test signal to be applied to the device under test; a first driver that is electrically connected to a terminal of the device under test and that supplies the test signal to the terminal of the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the test signal occurring until the test signal reaches the terminal of the device under test; and a second driver that is electrically connected to the terminal of the device under test and that supplies the correction signal to the terminal of the device under test.
摘要翻译：提供了一种测试被测设备的测试设备，包括：测试信号产生部分，生成要应用于被测设备的测试信号; 第一驱动器，电连接到被测器件的端子，并将测试信号提供给被测器件的端子; 校正信号生成部，其生成用于校正测试信号的衰减的校正信号，直到测试信号到达被测器件的端子为止; 以及第二驱动器，其电连接到被测器件的端子，并将校正信号提供给被测器件的端子。

3. 发明授权

US08014969B2 Test apparatus, test method and manufacturing method 失效
标题翻译：试验装置，试验方法及制造方法
公开(公告)号：US08014969B2
公开(公告)日：2011-09-06
申请号：US11964719
申请日：2007-12-27
申请人： Hirokatsu Niijima , Koji Hara , Noriyoshi Kozuka , Kohei Shibata , Tetsuya Sakaniwa
发明人： Hirokatsu Niijima , Koji Hara , Noriyoshi Kozuka , Kohei Shibata , Tetsuya Sakaniwa
IPC分类号： G01D3/00
CPC分类号： G01R31/31928 , G01R31/31917 , G11C29/56 , G11C2029/5602
摘要： There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.
摘要翻译：提供了一种用于测试多个待测设备的测试装置。该测试装置包括信号输入部分，该信号输入部分向被测器件施加测试信号，以使被测器件同时输出响应信号;组合部分，通过使用从器件输出的响应信号产生单个组合信号以及判定部，判断被测设备是否参照组合信号正常工作。

4. 发明申请

US20110063006A1 TIMING VERNIER USING A DELAY LOCKED LOOP 失效
标题翻译：使用延时锁定的定时器
公开(公告)号：US20110063006A1
公开(公告)日：2011-03-17
申请号：US12950305
申请日：2010-11-19
申请人： Bruce MILLAR
发明人： Bruce MILLAR
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , G01R31/31922 , G01R31/31928 , H03K5/135 , H03K5/1565 , H03K2005/00071 , H03L7/0812 , H03L7/0891
摘要： A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal.
摘要翻译：一种用于使多个可编程定时游标与参考脉冲信号同步的方法，每个游标可编程为由施加到偏置输入的控制信号确定的延迟范围内的多个定时步骤中的一个。从多个游标中选择第一和第二控制游标，将第一控制游标编程为第一延迟，并将第二控制游标编程为第二延迟。第一和第二控制游标被一起触发以产生相应的第一和第二延迟信号。以对应于所生成的第一延迟信号和第二延迟信号之间的差的占空比产生差分脉冲信号。将脉冲信号的占空比与参考脉冲信号的占空比进行比较，以产生差分信号脉冲。差分信号脉冲耦合到游标的偏置输入端以调整延迟范围，使得差分信号的占空比接近参考脉冲信号的占空比。

5. 发明授权

US07863954B2 Timing vernier using a delay locked loop 有权
标题翻译：定时游标使用延迟锁定循环
公开(公告)号：US07863954B2
公开(公告)日：2011-01-04
申请号：US12687541
申请日：2010-01-14
申请人： Bruce Millar
发明人： Bruce Millar
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , G01R31/31922 , G01R31/31928 , H03K5/135 , H03K5/1565 , H03K2005/00071 , H03L7/0812 , H03L7/0891
摘要： A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In one embodiment there is provided a circuit for implementing the method.
摘要翻译：一种用于使多个可编程定时游标与参考脉冲信号同步的方法，每个游标可编程为由施加到偏置输入的控制信号确定的延迟范围内的多个定时步骤中的一个。从多个游标中选择第一和第二控制游标，将第一控制游标编程为第一延迟，并将第二控制游标编程为第二延迟。第一和第二控制游标被一起触发以产生相应的第一和第二延迟信号。以对应于所生成的第一延迟信号和第二延迟信号之间的差的占空比产生差分脉冲信号。将脉冲信号的占空比与参考脉冲信号的占空比进行比较，以产生差分信号脉冲。差分信号脉冲耦合到游标的偏置输入端以调整延迟范围，使得差分信号的占空比接近参考脉冲信号的占空比。在一个实施例中，提供了一种用于实现该方法的电路。

6. 发明授权

US07759927B2 Test apparatus and testing method 失效
标题翻译：测试仪器和测试方法
公开(公告)号：US07759927B2
公开(公告)日：2010-07-20
申请号：US11594418
申请日：2006-11-08
申请人： Nobuei Washizu
发明人： Nobuei Washizu
IPC分类号： H03D13/00
CPC分类号： G01R31/3191 , G01R31/31922 , G01R31/31928
摘要： There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is almost equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.
摘要翻译：提供了一种用于测试被测器件的测试装置，具有用于产生用于控制被测器件的操作的参考时钟的参考时钟源，用于基于相位调整信号产生的时钟再生电路输入的再生时钟，其频率与参考时钟几乎相等，并且具有与对应于相位调整信号的参考时钟的相位差;定时比较器，用于获得从被测器件输出的输出信号的值，基于再生时钟，第一相位比较部分，用于输出基于输出信号和再生时钟的相位的比较结果将相位差收敛到预先设定的参考相位差的相位调整信号，以及存储部分，用于顺序地存储从第一相位比较部分输出的相位调整信号。

7. 发明授权

US07676715B2 Integrated circuit with continuous testing of repetitive functional blocks 有权
标题翻译：具有连续测试重复功能块的集成电路
公开(公告)号：US07676715B2
公开(公告)日：2010-03-09
申请号：US11755448
申请日：2007-05-30
申请人： Gary L. Miller , Hugo Mauro V D C Cavalcanti
发明人： Gary L. Miller , Hugo Mauro V D C Cavalcanti
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/31928 , G01R31/31926
摘要： A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing, substituting a test repetitive functional block for a selected repetitive functional block, and testing the selected repetitive functional block during normal functional mode of the IC. An IC which includes repetitive functional blocks for performing corresponding functional block operations during normal functional mode of the IC, and a test system which performs continuous testing of each repetitive functional block while the functional block operations are performed during normal functional mode of the IC. One block may be tested during normal operation for each IC reset event without transferring or copying state information. Multiple blocks may be tested one at a time during normal operation by transferring state information between a selected block and a test block.
摘要翻译：一种连续测试集成电路（IC）上提供的重复功能块的方法，包括一次选择一个重复功能块进行测试，将测试重复功能块替换为所选择的重复功能块，并测试所选重复功能块功能块在IC的正常功能模式下。一种IC，其包括用于在IC的正常功能模式期间执行相应的功能块操作的重复功能块，以及在IC的正常功能模式期间执行功能块操作时对每个重复功能块执行连续测试的测试系统。在每个IC复位事件的正常操作期间可以测试一个块，而不转移或复制状态信息。在正常操作期间可以通过在所选块和测试块之间传送状态信息来一次测试多个块。

8. 发明授权

US07538582B2 Driver circuit, test apparatus and adjusting method 有权
标题翻译：驱动电路，测试仪器及调整方法
公开(公告)号：US07538582B2
公开(公告)日：2009-05-26
申请号：US11262507
申请日：2005-10-28
申请人： Naoki Matsumoto , Takashi Sekino , Toshiaki Awaji
发明人： Naoki Matsumoto , Takashi Sekino , Toshiaki Awaji
IPC分类号： H03K19/094
CPC分类号： G01R31/31928 , G01R31/31924
摘要： A test apparatus for testing a device under test is provided. The test apparatus includes a test signal generating section for generating a test signal to be provided to the device under test, a driver circuit for providing the test signal to the device under test and a determination section for determining whether is good or bad of the device under test based on the output signal outputted by the device under test according to the test signal. The driver circuit includes a main driver and a sub-driver for outputting drive signals according to the test signal, respectively, a differentiating circuit for outputting a differentiated signal obtained by differentiating the drive signal outputted by the sub-driver and an adding section for providing a signal having the waveform according to the test signal which is obtained by adding the differentiated signal to the drive signal outputted by the main driver to the device under test.
摘要翻译：提供了一种用于测试被测设备的测试设备。测试装置包括：测试信号产生部分，用于产生要提供给被测设备的测试信号;驱动器电路，用于将测试信号提供给被测器件;以及确定部分，用于确定器件的良好或坏根据被测设备根据测试信号输出的输出信号进行测试。驱动器电路包括主驱动器和副驱动器，用于分别根据测试信号输出驱动信号;差分电路，用于输出通过对由子驱动器输出的驱动信号进行微分而获得的微分信号;以及加法部分，用于提供具有根据测试信号的波形的信号，该信号通过将微分信号与由主驱动器输出的驱动信号相加到被测器件而获得。

9. 发明授权

US07532994B2 Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method 失效
标题翻译：试验装置，试验方法，电子装置制造方法，试验模拟装置及试验模拟方法
公开(公告)号：US07532994B2
公开(公告)日：2009-05-12
申请号：US11395094
申请日：2006-03-31
申请人： Hideki Tada , Mitsuo Hori , Takahiro Kataoka , Hiroyuki Sekiguchi
发明人： Hideki Tada , Mitsuo Hori , Takahiro Kataoka , Hiroyuki Sekiguchi
IPC分类号： G01R27/28
CPC分类号： G01R31/31932 , G01R31/31928 , G01R31/31937
摘要： A test apparatus for testing an electronic device by providing test signals to the electronic device and comparing multiple output signals with respective anticipated values is disclosed, the test apparatus including: a reference timing detecting unit for detecting that one of the output signals has changed; a setting unit for setting beforehand a minimum time from changing of the output signal to changing of another output signal; an acquisition unit for acquiring the value of the latter output signal at a timing at which the minimum time has elapsed from detection of change of the former output signal; and a determination unit for determining the electronic device to be defective in the event that the value of the latter output signal thus acquired does not match the value which the latter output signal should assume following elapsing of the minimum time.
摘要翻译：公开了一种用于通过向电子设备提供测试信号并将多个输出信号与各自的预期值进行比较来测试电子设备的测试设备，该测试设备包括：用于检测输出信号中的一个已经改变的参考定时检测单元; 设置单元，用于预先设置从输出信号的改变到另一个输出信号的改变的最小时间; 获取单元，用于在从前一个输出信号的改变的检测经过最小时间的定时获取后一个输出信号的值; 以及确定单元，用于在如此获取的后一个输出信号的值与后一个输出信号应该在最小时间之后应该呈现的值不匹配的情况下确定该电子设备是有缺陷的。

10. 发明授权

US07500148B2 Test apparatus and testing method 有权
标题翻译：测试仪器和测试方法
公开(公告)号：US07500148B2
公开(公告)日：2009-03-03
申请号：US11180972
申请日：2005-07-13
申请人： Kiyoshi Murata
发明人： Kiyoshi Murata
IPC分类号： G06F11/00
CPC分类号： G01R31/31928 , G01R31/31924
摘要： There is provided a testing apparatus that tests a device under test. The testing apparatus includes: a command executing unit operable to sequentially execute commands included in a test program for the device under test every command cycle; a test pattern memory operable to store pattern length identifying information identifying a pattern length of a test pattern sequence being output during a command cycle period executing the command and the test pattern sequence, in association with each command; a test pattern memory reading unit operable to read a test pattern sequence of a length corresponding to the pattern length identifying information stored on the test pattern memory in association with one command from the test pattern memory when the one command is executed; and a test pattern outputting unit operable to output the test pattern sequence read by the test pattern memory reading unit in association with the one command to a terminal of the device under test during a command cycle period executing the one command.
摘要翻译：提供了测试被测设备的测试装置。该测试装置包括：命令执行单元，用于对每个命令循环中的被测设备执行包含在测试程序中的命令; 测试模式存储器，用于存储识别在执行命令和测试模式序列的命令循环周期期间输出的测试模式序列的模式长度的模式长度识别信息，与每个命令相关联; 测试图形存储器读取单元，用于当执行所述一个命令时，从所述测试图形存储器读取与来自所述测试图形存储器的一个命令相关联的与存储在所述测试图案存储器上的图案长度识别信息相对应的长度的测试图案序以及测试图案输出单元，其可操作以在执行所述一个命令的命令循环周期期间将由所述测试图案存储器读取单元读取的所述测试图案序列与所述一个命令相关联地输出到被测设备的终端。

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