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1. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

2. 发明申请

US20120117211A1 Fencing Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer 有权
标题翻译：并行计算机并行主动消息接口中的击剑数据传输
公开(公告)号：US20120117211A1
公开(公告)日：2012-05-10
申请号：US12940198
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F15/16
CPC分类号： G06F9/546 , G06F15/16 , H04L67/40
摘要： Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint comprising a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task, the compute nodes coupled for data communications through the PAMI and through data communications resources including a deterministic data communications network, including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endpoints.
摘要翻译：在并行计算机的并行活动消息接口（“PAMI”）中的防护数据传输，PAMI包括数据通信端点，每个端点包括用于计算节点上的执行线程的数据通信参数的规范，包括客户端的规范，上下文和任务，所述计算节点被耦合用于通过PAMI的数据通信，并且通过包括确定性数据通信网络的数据通信资源，包括通过PAMI启动执行有序SEND指令的有序序列，以在两个端点，影响确定性SEND数据传输; 并且通过PAMI执行，没有FENCE计算SEND数据传输，一个活动的FENCE指令，FENCE指令只有在完成在执行FENCE指令之前发起的所有SEND指令以完成执行，以在两个端点之间进行SEND数据传输。

3. 发明授权

US08527672B2 Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer 失效
标题翻译：在并行计算机的并行活动消息接口中，屏蔽直接存储器访问数据传输
公开(公告)号：US08527672B2
公开(公告)日：2013-09-03
申请号：US12940300
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F13/28 , G06F15/00 , G06F7/38
CPC分类号： G06F13/28
摘要： Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.
摘要翻译：在并行计算机的并行活动消息接口（“PAMI”）中的屏蔽直接存储器访问（'DMA'）数据传输，PAMI包括数据通信端点，每个端点包括客户端的规范，上下文和任务，通过PAMI和通过可操作地耦合到共享随机存取存储器的段的DMA控制器耦合的端点，DMA控制器通过该共享随机存取存储器确定性地传送数据通信，包括通过PAMI发起执行有序DMA指令的有序DMA指令，用于DMA数据传输两个端点，通过DMA控制器和一段共享存储器实现确定性DMA数据传输; 并且通过PAMI执行无FENCE计算DMA数据传输的有效FENCE指令，FENCE指令只有在完成在执行FENCE指令之前启动的所有DMA指令以完成执行，以在两个端点之间进行DMA数据传输。

4. 发明申请

US20120117281A1 Fencing Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer 失效
标题翻译：在并行计算机的并行主动消息接口中的击剑直接存储器访问数据传输
公开(公告)号：US20120117281A1
公开(公告)日：2012-05-10
申请号：US12940300
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.
摘要翻译：在并行计算机的并行活动消息接口（“PAMI”）中的屏蔽直接存储器访问（“DMA”）数据传输，PAMI包括数据通信端点，每个端点包括客户端的规范，上下文和任务，通过PAMI和通过可操作地耦合到共享随机存取存储器的段的DMA控制器耦合的端点，DMA控制器通过该共享随机存取存储器确定性地传送数据通信，包括通过PAMI发起执行有序DMA指令的有序DMA指令，用于DMA数据传输两个端点，通过DMA控制器和一段共享存储器实现确定性DMA数据传输; 并且通过PAMI执行无FENCE计算DMA数据传输的有效FENCE指令，FENCE指令只有在完成在执行FENCE指令之前启动的所有DMA指令以完成执行，以在两个端点之间进行DMA数据传输。

5. 发明申请

US20120117138A1 Fencing Network Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer 有权
标题翻译：击剑网络直接内存访问数据传输并行计算机的并行主动消息接口
公开(公告)号：US20120117138A1
公开(公告)日：2012-05-10
申请号：US12940282
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F15/16
CPC分类号： G06F15/16 , G06F9/544 , G06F9/546 , G06F15/17331 , H04L67/40
摘要： Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.
摘要翻译：在并行计算机的并行活动消息接口（“PAMI”）中的屏蔽直接存储器访问（“DMA”）数据传输，PAMI包括数据通信端点，每个端点包括客户端的规范，上下文和任务，通过PAMI和通过DMA控制器进行数据通信的端点，可操作地耦合到确定性数据通信网络，DMA控制器通过该确定性数据通信网络确定性地传送数据通信，包括通过PAMI启动执行有序DMA指令的有序序列的DMA数据传输端点，通过DMA控制器和确定性数据通信网络实现确定性DMA数据传输; 并且通过PAMI执行无FENCE计算DMA数据传输的有效FENCE指令，FENCE指令只有在完成在执行FENCE指令之前启动的所有DMA指令以完成执行，以在两个端点之间进行DMA数据传输。

6. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

7. 发明授权

US09075759B2 Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer 有权
公开(公告)号：US09075759B2
公开(公告)日：2015-07-07
申请号：US12940282
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F15/16 , G06F15/173 , G06F7/38 , H04L29/06 , G06F9/54
CPC分类号： G06F15/16 , G06F9/544 , G06F9/546 , G06F15/17331 , H04L67/40
摘要： Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

8. 发明申请

US20120117137A1 Fencing Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer 有权
标题翻译：并行计算机并行主动消息接口中的击剑数据传输
公开(公告)号：US20120117137A1
公开(公告)日：2012-05-10
申请号：US12940259
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F15/16
CPC分类号： G06F9/546 , G06F9/544 , G06F15/16 , G06F15/17331 , H04L67/40
摘要： Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task; the compute nodes coupled for data communications through the PAMI and through data communications resources including at least one segment of shared random access memory; including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers through a segment of shared memory; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endpoints.
摘要翻译：在并行计算机的并行活动消息接口（“PAMI”）中的防护数据传输，PAMI包括数据通信端点，每个端点包括计算节点上的执行线程的数据通信参数的规范，包括客户端的规范，背景和任务; 所述计算节点被耦合用于通过所述PAMI的数据通信，并且通过包括至少一个共享随机存取存储器段的数据通信资源; 包括通过PAMI启动对两个端点之间的SEND数据传输的有效SEND指令序列的执行，通过一段共享存储器实现确定性SEND数据传输; 并且通过PAMI执行，没有FENCE计算SEND数据传输，一个活动的FENCE指令，FENCE指令只有在完成在执行FENCE指令之前发起的所有SEND指令以完成执行，以在两个端点之间进行SEND数据传输。

9. 发明授权

US09069631B2 Fencing data transfers in a parallel active messaging interface of a parallel computer 有权
标题翻译：并行计算机的并行活动消息接口中的防护数据传输
公开(公告)号：US09069631B2
公开(公告)日：2015-06-30
申请号：US12940198
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F15/16 , G06F15/173 , G06F7/38 , G06F9/54 , H04L29/06
CPC分类号： G06F9/546 , G06F15/16 , H04L67/40
摘要： Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint comprising a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task, the compute nodes coupled for data communications through the PAMI and through data communications resources including a deterministic data communications network, including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endpoints.
摘要翻译：在并行计算机的并行活动消息接口（“PAMI”）中的防护数据传输，PAMI包括数据通信端点，每个端点包括用于计算节点上的执行线程的数据通信参数的规范，包括客户端的规范，上下文和任务，所述计算节点被耦合用于通过PAMI的数据通信，并且通过包括确定性数据通信网络的数据通信资源，包括通过PAMI启动执行有序SEND指令的有序序列，以在两个端点，影响确定性SEND数据传输; 并且通过PAMI执行，没有FENCE计算SEND数据传输，一个活动的FENCE指令，FENCE指令只有在完成在执行FENCE指令之前发起的所有SEND指令以完成执行，以在两个端点之间进行SEND数据传输。

10. 发明授权

US09052974B2 Fencing data transfers in a parallel active messaging interface of a parallel computer 有权
公开(公告)号：US09052974B2
公开(公告)日：2015-06-09
申请号：US12940259
申请日：2010-11-05
申请人： Michael A. Blocksome , Amith R. Mamidala
发明人： Michael A. Blocksome , Amith R. Mamidala
IPC分类号： G06F15/16 , G06F7/38 , G06F9/54 , H04L29/06 , G06F15/173
CPC分类号： G06F9/546 , G06F9/544 , G06F15/16 , G06F15/17331 , H04L67/40
摘要： Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task; the compute nodes coupled for data communications through the PAMI and through data communications resources including at least one segment of shared random access memory; including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers through a segment of shared memory; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endpoints.

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