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1. 发明授权

US07804728B2 Information handling system with SRAM precharge power conservation 失效
标题翻译：具有SRAM预充电功能的信息处理系统
公开(公告)号：US07804728B2
公开(公告)日：2010-09-28
申请号：US12185234
申请日：2008-08-04
申请人： Michael Ju Hyeok Lee , Bao G Truong
发明人： Michael Ju Hyeok Lee , Bao G Truong
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C11/413
摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.
摘要翻译：信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。读取操作可以遵循预充电操作或均衡位线电压操作。如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。

2. 发明申请

US20130141997A1 SINGLE-ENDED VOLATILE MEMORY ACCESS 审中-公开
标题翻译：单端永久存储器访问
公开(公告)号：US20130141997A1
公开(公告)日：2013-06-06
申请号：US13312945
申请日：2011-12-06
申请人： Michael Ju Hyeok Lee , Bao G. Truong
发明人： Michael Ju Hyeok Lee , Bao G. Truong
IPC分类号： G11C7/12 , G11C8/08 , G11C8/00
CPC分类号： G11C14/0054 , G11C7/067 , G11C8/00 , G11C8/08 , G11C11/419
摘要： A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy.
摘要翻译：存储器包括形成行和列的存储器单元阵列。行包括存储单元对。存储器单元可以包括耦合到交叉耦合的反相器的交替侧的两个交叉耦合的反相器和两个通过装置。对于读取操作，字线驱动电路选择该对中的一个存储单元，所选择的存储单元是寻址存储单元，而剩余单元是未寻址存储单元。响应于字线使能信号，寻址的存储器单元中的通过门经由补充位线将寻址的存储器单元耦合到评估门，其从读取操作中解析数据。在读取操作期间，未寻址存储器单元经由另一个通道耦合到真正的位线，该位线在没有评估门的情况下终止以节省能量。

3. 发明申请

US20130141992A1 VOLATILE MEMORY ACCESS VIA SHARED BITLINES 审中-公开
标题翻译：挥发性存储器通过共享的双绞线
公开(公告)号：US20130141992A1
公开(公告)日：2013-06-06
申请号：US13312867
申请日：2011-12-06
申请人： Michael Ju Hyeok Lee , Bao G. Truong
发明人： Michael Ju Hyeok Lee , Bao G. Truong
IPC分类号： G11C7/00
CPC分类号： G11C14/0054 , G11C7/18 , G11C11/419
摘要： A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.
摘要翻译：存储器包括形成行和列的存储器单元阵列。阵列的行包括存储单元对。存储器单元可以包括耦合到交叉耦合的反相器的交替侧的两个交叉耦合的反相器和两个通过装置。存储器单元对的两个存储单元共享共同的对内位线。相邻的存储单元对共享一个共同的对对位线。为了对阵列的行和列中的存储单元对中的特定存储器单元执行数据读取操作，字线驱动电路传输字线激活信号以选择用于数据读取操作的行和该对中的特定一个用于数据读取操作的存储单元。

4. 发明申请

US20100027361A1 Information Handling System with SRAM Precharge Power Conservation 失效
标题翻译：具有SRAM预充电功能的信息处理系统
公开(公告)号：US20100027361A1
公开(公告)日：2010-02-04
申请号：US12185234
申请日：2008-08-04
申请人： Michael Ju Hyeok Lee , Bao G. Truong
发明人： Michael Ju Hyeok Lee , Bao G. Truong
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/413
摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.
摘要翻译：信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。读取操作可以遵循预充电操作或均衡位线电压操作。如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。

5. 发明授权

US07813189B2 Array data input latch and data clocking scheme 失效
标题翻译：阵列数据输入锁存器和数据时钟方案
公开(公告)号：US07813189B2
公开(公告)日：2010-10-12
申请号：US12166421
申请日：2008-07-02
申请人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
发明人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译：一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。

6. 发明授权

US07015723B2 Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation 失效
标题翻译：动态静态逻辑控制元件，用于发出控制信号结束与逻辑评估之间的间隔
公开(公告)号：US07015723B2
公开(公告)日：2006-03-21
申请号：US10922271
申请日：2004-08-19
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.
摘要翻译：用于发信号通知控制信号的结束与逻辑评估之间的间隔的动态静态逻辑控制元件提供紧凑的电路，用于阻止动态逻辑门的未评估状态的指示，直到控制信号结束为止。控制信号连接到控制元件的预充电输入，并且求和节点经由逆变器连接到一个或多个评估树和控制元件输出。逆变器连接到超控电路，其将控制元件的输出强制到与预充电状态相反的状态，直到控制信号结束。然后，控制元件的输出呈现与预充电状态相对应的状态，直到评估发生。因此，控制元件输出产生指示控制信号的结束与评估之间的间隔的窗口信号。

7. 发明授权

US07002860B2 Multilevel register-file bit-read method and apparatus 有权
标题翻译：多级寄存器 - 文件位读取方法和装置
公开(公告)号：US07002860B2
公开(公告)日：2006-02-21
申请号：US10703017
申请日：2003-11-06
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C7/12 , G11C8/00 , G11C11/41
CPC分类号： G11C7/1012 , G11C7/1051 , G11C8/10
摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.
摘要翻译：位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。选择器处于耦合到相应输出节点的Q组中。每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。用于N + 1个多路复用器的输出逻辑门分别具有分别耦合到R个节点的R个输入。多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。

8. 发明授权

US6107852A Method and device for the reduction of latch insertion delay 失效
标题翻译：用于减少锁存器插入延迟的方法和装置
公开(公告)号：US6107852A
公开(公告)日：2000-08-22
申请号：US81001
申请日：1998-05-19
申请人： Christopher McCall Durham , Michael Ju Hyeok Lee , Visweswara Rao Kodali , Harsh Dev Sharma
发明人： Christopher McCall Durham , Michael Ju Hyeok Lee , Visweswara Rao Kodali , Harsh Dev Sharma
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356156
摘要： A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
摘要翻译：公开了一种用于减少与用于在数据处理系统中实现集成电路的电路中插入锁存相关联的惩罚的方法和装置。公开了一种半导体器件，其包括主锁存电路，反馈锁存电路和输出端子。主锁存电路能够接收输入数据信号和输入时钟信号。主锁存电路根据输入数据和时钟信号产生锁存输出信号。反馈锁存电路能够接收来自主锁存电路的锁存输出信号并存储锁存器输出信号。反馈锁存电路能够产生由主锁存电路接收的反馈锁存电路输出信号，以维持锁存输出信号。设备的输出端耦合到反馈锁存电路，用于输出等于反馈锁存电路输出信号的器件输出信号。

9. 发明授权

US6046606A Soft error protected dynamic circuit 失效
标题翻译：软错误保护动态电路
公开(公告)号：US6046606A
公开(公告)日：2000-04-04
申请号：US10200
申请日：1998-01-21
申请人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
发明人： Sam Gat-Shang Chu , Visweswara Rao Kodali , Michael Ju Hyeok Lee
IPC分类号： H03K19/003 , G06F11/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F11/00 , G06F11/004
摘要： A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit. The cross-coupled PFET device is operable to sense an initiated untimely switching action in the upper circuit and effect a re-application of the holding PFET in the upper circuit to re-establish the appropriate logic potential levels in the upper circuit.
摘要翻译：尽管存在α粒子碰撞，但是方法和装置有效地保持逻辑电路中的逻辑状态电位电平。包括有源器件的交叉耦合电路在互补逻辑电路装置中实现，以在诸如可能由半导体逻辑电路的α粒子碰撞引起的切换的过早切换的情况下保持当前逻辑值。稳定晶体管开关器件被布置为感测不适当或过早的开关启动，并通过操作来响应于其来维持逻辑电路内的适当的逻辑电平。在一个实施例中，双轨逻辑电路中的上电路的内部节点连接到下电路中的交叉耦合PFET器件的栅极端子。交叉耦合PFET器件可操作以感测上电路中引发的不合时宜的开关动作，并且实现上电路中保持PFET的重新施加，以重新建立上电路中适当的逻辑电位电平。

10. 发明授权

US07552413B2 System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model 有权
标题翻译：系统和计算机程序，用于通过模拟完整阵列模型中边缘单元的操作来验证阵列的性能
公开(公告)号：US07552413B2
公开(公告)日：2009-06-23
申请号：US12166811
申请日：2008-07-02
申请人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
发明人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
IPC分类号： G06F17/50 , G11C29/00
CPC分类号： G06F17/5022
摘要： A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的系统和计算机程序减少了完整设计验证所需的计算时间。阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。观察到字线到达以确定最坏情况行进行选择。对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

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