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1. 发明申请

US20070008797A1 Data input and data output control device and method 有权
标题翻译：数据输入和数据输出控制装置及方法
公开(公告)号：US20070008797A1
公开(公告)日：2007-01-11
申请号：US11430281
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1063 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： A data input and data output control device and method in which a plurality of write or read data composed of m (2n+k) bits (where m, n, and k are all integers) may be accessed within one clock of external input clock.
摘要翻译：一种数据输入和数据输出控制装置和方法，其中由m（2＆gt; n + k）位（其中m，n和k都是整数）组成的多个写入或读取数据可以是在外部输入时钟的一个时钟内访问。

2. 发明授权

US07522440B2 Data input and data output control device and method 有权
标题翻译：数据输入和数据输出控制装置及方法
公开(公告)号：US07522440B2
公开(公告)日：2009-04-21
申请号：US11430281
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： G11C5/02
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1063 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： A data input and data output control device and method in which a plurality of write or read data composed of m (2n+k) bits (where m, n, and k are all integers) may be accessed within one clock of external input clock.
摘要翻译：一种数据输入和数据输出控制装置和方法，其中可以在外部输入时钟的一个时钟内访问由m（2n + k）位（其中m，n和k都是整数）组成的多个写入或读取数据。

3. 发明授权

US07420870B2 Phase locked loop circuit and method of locking a phase 有权
标题翻译：锁相环电路及锁相方法
公开(公告)号：US07420870B2
公开(公告)日：2008-09-02
申请号：US11430199
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： G11C8/02 , H03L7/06
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133 , H03L7/089 , H03L7/0891 , H03L7/093
摘要： A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.
摘要翻译：一种锁相环电路及锁相方法。相位锁定环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并在相位为外部时钟信号滞后于反馈时钟信号的相位，环路滤波器电路响应于上升信号增加控制电压，并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压和直接产生n个（其中n是整数> = 4）内部时钟信号。相位锁定环路电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。

4. 发明申请

US20060284657A1 Phase locked loop circuit and method of locking a phase 有权
标题翻译：锁相环电路及锁相方法
公开(公告)号：US20060284657A1
公开(公告)日：2006-12-21
申请号：US11430199
申请日：2006-05-09
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133 , H03L7/089 , H03L7/0891 , H03L7/093
摘要： A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.
摘要翻译：一种锁相环电路及锁相方法。相位锁定环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并在相位为外部时钟信号滞后于反馈时钟信号的相位，环路滤波器电路响应于上升信号增加控制电压，并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压和直接产生n个（其中n是整数> = 4）内部时钟信号。相位锁定环路电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。

5. 发明申请

US20070109032A1 Charge pump circuit and method thereof 审中-公开
标题翻译：电荷泵电路及其方法
公开(公告)号：US20070109032A1
公开(公告)日：2007-05-17
申请号：US11598047
申请日：2006-11-13
申请人： Moon-Sook Park , Kyu-Hyoun Kim
发明人： Moon-Sook Park , Kyu-Hyoun Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H03L7/0812
摘要： A charge pump circuit and method thereof are provided. The example charge pump may include a first switch transistor supplying a first current to an output node in response to a first signal to increase a level of current at the output node, a second switch transistor sinking a second current from the output node in response to a second signal to decrease a level of current at the output node and a controller reducing an amount of the first and second currents if the first and second currents are generated concurrently. The example method may include supplying a first current to an output node in response to a first signal to increase a level of current at the output node, sinking a second current from the output node in response to a second signal to decrease a level of current at the output node and reducing an amount of the first and second currents if the first and second currents are generated concurrently.
摘要翻译：提供一种电荷泵电路及其方法。示例电荷泵可以包括响应于第一信号向输出节点提供第一电流以提高输出节点处的电流电平的第一开关晶体管，响应于第二开关晶体管从输出节点吸收第二电流第二信号，用于降低输出节点处的电流电平;以及控制器，如果同时产生第一和第二电流，则减少第一和第二电流的量。示例性方法可以包括响应于第一信号向输出节点提供第一电流以增加输出节点处的电流电平，响应于第二信号从输出节点吸收第二电流以降低电流电平并且如果同时产生第一和第二电流，则减少第一和第二电流的量。

6. 发明授权

US09076770B2 Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same 有权
标题翻译：集成电路芯片堆叠具有最初相同的裸片，其具有熔丝和其制造方法
公开(公告)号：US09076770B2
公开(公告)日：2015-07-07
申请号：US13569267
申请日：2012-08-08
申请人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
IPC分类号： H01L23/48 , H01L23/525 , H01L25/065 , H01L25/00 , H01L25/18
CPC分类号： H01L23/481 , H01L23/5256 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
摘要翻译：具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上吹入保险丝来个性化，将先前通过熔断保险丝连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具在第二次死亡时死于TSV。

7. 发明授权

US08756475B2 Method of detecting error in a semiconductor memory device 有权
标题翻译：检测半导体存储器件中的误差的方法
公开(公告)号：US08756475B2
公开(公告)日：2014-06-17
申请号：US12929250
申请日：2011-01-11
申请人： Hoe-Ju Chung , Kyu-Hyoun Kim
发明人： Hoe-Ju Chung , Kyu-Hyoun Kim
IPC分类号： H03M13/00 , H03M13/29 , G06F11/08
CPC分类号： H03M13/29 , G06F11/08 , G06F11/1008 , G11C7/1006 , G11C29/42 , G11C2029/0411 , G11C2207/104
摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.
摘要翻译：提供一种半导体存储器件和包括该半导体存储器件的存储器系统。半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生第二最终错误检测信号。

8. 发明授权

US07212052B2 Jitter suppressing delay locked loop circuits and related methods 失效
标题翻译：抖动抑制延迟锁定环路电路及相关方法
公开(公告)号：US07212052B2
公开(公告)日：2007-05-01
申请号：US10925522
申请日：2004-08-25
申请人： Kyu-Hyoun Kim
发明人： Kyu-Hyoun Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.
摘要翻译：提供延迟锁定环路电路，其包括产生延迟锁定环路输出信号的延迟锁定环路和抖动抑制器。抖动抑制器可以包括延迟电路，其接收延迟锁定环路输出信号并产生延迟锁定环路输出信号的一个或多个延迟版本;以及相位插值器，其接收延迟锁定环路输出信号和一个或多个延迟锁定环路输出信号延迟锁定环路输出信号。在本发明的某些实施例中，延迟电路可以包括多个串联连接的延迟单元。这些延迟单元中的每一个可以在等于输入到延迟锁定环路的外部时钟信号的一个时钟周期的时间延迟输入的信号。

9. 发明申请

US20050122149A1 Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals 失效
标题翻译：适用于延迟锁定环路的占空比校正电路以及校正周期信号占空比的方法
公开(公告)号：US20050122149A1
公开(公告)日：2005-06-09
申请号：US11005821
申请日：2004-12-07
申请人： Geun-Hee Cho , Kyu-Hyoun Kim
发明人： Geun-Hee Cho , Kyu-Hyoun Kim
IPC分类号： G11C8/00 , H03K5/04 , H03K5/135 , H03K5/151 , H03K5/156 , H03L7/081
CPC分类号： H03K5/151 , H03K5/135 , H03K5/1565 , H03L7/0812
摘要： Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.
摘要翻译：延迟锁定环集成电路包括占空比校正电路。该占空比校正电路响应于具有不均匀占空比的至少一个输入时钟信号而产生具有基本均匀的占空比的至少一个输出时钟信号。占空比校正电路还响应于在占空比校正电路内同步省电占空比更新操作的定时的待机控制信号。这些更新操作重置校正电路的设定点。

10. 发明申请

US20050053120A1 Spread spectrum clock generator 失效
标题翻译：扩频时钟发生器
公开(公告)号：US20050053120A1
公开(公告)日：2005-03-10
申请号：US10837391
申请日：2004-04-29
申请人： Kyu-Hyoun Kim , Hoe-Ju Chung
发明人： Kyu-Hyoun Kim , Hoe-Ju Chung
IPC分类号： H03K5/1252 , G06F1/08 , H03K5/00 , H03K5/13 , H03K5/156 , H04B1/69 , H04B15/02
CPC分类号： H04B15/02 , G06F1/08 , H03K5/133 , H03K5/156 , H03K2005/00071 , H04B2215/067
摘要： A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.
摘要翻译：扩频时钟发生器包括用于存储对应于预定延迟的控制码的非易失性存储器。延迟电路在一段时间内接收具有确定延迟的预定位数的控制码，以应用于固定时钟信号。该延迟减轻了周期性时钟信号引起的电磁干扰。

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