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1. 发明授权

US09058896B2 DRAM refresh 有权
标题翻译： DRAM刷新
公开(公告)号：US09058896B2
公开(公告)日：2015-06-16
申请号：US13598001
申请日：2012-08-29
申请人： Michele M. Franceschini , Hillery Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-Hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Hillery Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-Hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
IPC分类号： G11C7/00 , G11C11/406 , G11C29/50
CPC分类号： G11C11/40622 , G11C29/50016 , G11C2211/4065 , G11C2211/4068
摘要： A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.
摘要翻译：具有至少具有快速和慢刷新速率的DRAM的刷新包括用具有刷新信息的行或行编码指针，读取刷新信息，以及用刷新信息递增快速刷新地址计数器。刷新可以通过对可能需要快速刷新的行上的一个或多个单元进行编码来执行，一组或多个单元可以需要快速刷新，或者一行上的一个或多个单元可以不需要快速刷新

2. 发明授权

US08718216B2 Digital phase detector with zero phase offset 失效
公开(公告)号：US08718216B2
公开(公告)日：2014-05-06
申请号：US13242053
申请日：2011-09-23
申请人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： H03D3/24
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

3. 发明申请

US20140063997A1 DRAM REFRESH 有权
标题翻译： DRAM刷新
公开(公告)号：US20140063997A1
公开(公告)日：2014-03-06
申请号：US13598001
申请日：2012-08-29
申请人： Michele M. Franceschini , Hillery Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-Hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Hillery Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-Hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
IPC分类号： G11C11/402 , G11C29/00
CPC分类号： G11C11/40622 , G11C29/50016 , G11C2211/4065 , G11C2211/4068
摘要： A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.
摘要翻译：具有至少具有快速和慢刷新速率的DRAM的刷新包括用具有刷新信息的行或行编码指针，读取刷新信息，以及用刷新信息递增快速刷新地址计数器。刷新可以通过对可能需要快速刷新的行上的一个或多个单元进行编码来执行，一组或多个单元可以需要快速刷新，或者一行上的一个或多个单元可以不需要快速刷新

4. 发明申请

US20140043927A1 METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM 有权
标题翻译：用于优化DRAM刷新速率的方法
公开(公告)号：US20140043927A1
公开(公告)日：2014-02-13
申请号：US13569486
申请日：2012-08-08
申请人： Michele M. Franceschini , Hillery Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-Hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Hillery Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-Hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
IPC分类号： G11C29/52 , G11C7/00
CPC分类号： G11C29/50 , G11C11/406 , G11C29/023 , G11C29/028 , G11C29/50016
摘要： A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.
摘要翻译：用于确定优化的刷新速率的方法涉及测试单元行的刷新率，确定行的错误率，评估行的错误率; 并重复这些步骤以减少刷新率，直到错误率大于约束，此时设置较慢的刷新率。

5. 发明授权

US08639874B2 Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device 失效
标题翻译：通过向DRAM设备发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理
公开(公告)号：US08639874B2
公开(公告)日：2014-01-28
申请号：US12341515
申请日：2008-12-22
申请人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
发明人： Warren Edward Maule , Kevin C. Gower , Kyu-hyoun Kim , Dustin James VanStee
IPC分类号： G06F12/06
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译：一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态，并激活用于将存储器单元作为正常的有源或备用设备读/写。

6. 发明申请

US20130313705A1 IMPLEMENTING DECOUPLING DEVICES INSIDE A TSV DRAM STACK 失效
标题翻译：在TSV DRAM堆栈中实现解码器件
公开(公告)号：US20130313705A1
公开(公告)日：2013-11-28
申请号：US13477371
申请日：2012-05-22
申请人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
发明人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
摘要翻译：提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。在提供绝缘体的DRAM的顶部和底部都生长玻璃层。在提供导体的每个玻璃层上生长一层金属。金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。

7. 发明授权

US08452919B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08452919B2
公开(公告)日：2013-05-28
申请号：US13567357
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

8. 发明授权

US08343804B2 Implementing multiple different types of dies for memory stacking 有权
标题翻译：实现多种不同类型的模具进行内存堆叠
公开(公告)号：US08343804B2
公开(公告)日：2013-01-01
申请号：US13364346
申请日：2012-02-02
申请人： Paul W. Coteus , Kyu-hyoun Kim
发明人： Paul W. Coteus , Kyu-hyoun Kim
IPC分类号： H01L21/00
CPC分类号： H01L24/73 , H01L23/481 , H01L24/06 , H01L24/48 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/10253 , H01L2924/1434 , H01L2924/15311 , H01L2224/45099 , H01L2924/00
摘要： A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.
摘要翻译：提供了一种用于实现用于存储器堆叠的多种不同类型的管芯的方法和结构。普通晶片具有预定的掩模版类型。标线型包括多个阵列和多个外围段。多个通硅通孔（TSV）被放置在阵列和外围段之间的边界处。基于从公共晶片选择划线的模具，获得用于存储器堆叠的多种不同类型的管芯。

9. 发明授权

US08310841B2 Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same 有权
标题翻译：具有最初相同的裸片的集成电路芯片堆叠具有开关个性化和制造它们的方法
公开(公告)号：US08310841B2
公开(公告)日：2012-11-13
申请号：US12617273
申请日：2009-11-12
申请人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L25/0657 , H01L23/481 , H01L25/18 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
摘要翻译：具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（TSV）的第二管芯最初相同，所述第一管芯通过在第一管芯上打开开关来个性化，先前通过开放式开关连接的TSV通过通孔（PTV），每个PTV实现通过第一管芯的导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过打开第二模具上的开关进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具在第二次死亡时死于TSV。

10. 发明申请

US20120151131A1 MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE 有权
标题翻译：具有可编程刷新周期的存储器系统
公开(公告)号：US20120151131A1
公开(公告)日：2012-06-14
申请号：US12963797
申请日：2010-12-09
申请人： Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
发明人： Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4065
摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.
摘要翻译：一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。响应于接收刷新命令刷新的存储器单元的数量是可编程的。

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