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1. 发明授权

US08001508B1 Method and system for analyzing input/output simultaneous switching noise 有权
标题翻译：分析输入/输出同时开关噪声的方法和系统
公开(公告)号：US08001508B1
公开(公告)日：2011-08-16
申请号：US11877072
申请日：2007-10-23
申请人： Nafira Daud , Geping Liu , San Wong , Lawrence David Smith
发明人： Nafira Daud , Geping Liu , San Wong , Lawrence David Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5072 , G06F2217/40 , G06F2217/82
摘要： A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.
摘要翻译：提供了一种用于优化集成电路的引脚选择的方法。引脚位置映射到向量。集成电路引脚之间的互感关系被捕获到矩阵中。矩阵包含每个引脚的信号状态如何影响I / O bank中其他引脚的切换的数据。将引脚位置和串扰矩阵组合起来，以表征引脚上串扰对引脚布置的影响。此后，用户可以决定改变引脚布置或改变引脚的采样间隔，以避免在串扰可能影响信号完整性时对引脚进行采样。该方法可以应用于影响信号完整性的多个同时开关噪声原因机制。在该实施例中，通过比较每个原因机制的影响来确定来自单独量化的原因机制的最坏情况引起机制。

2. 发明授权

US08504976B2 Empirical prediction of simultaneous switching noise 有权
标题翻译：同步开关噪声的实证预测
公开(公告)号：US08504976B2
公开(公告)日：2013-08-06
申请号：US13484136
申请日：2012-05-30
申请人： Zhuyuan Liu , Geping Liu , San Wong
发明人： Zhuyuan Liu , Geping Liu , San Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5054 , G06F2217/82
摘要： In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., αj). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.
摘要翻译：在示例实施例中，系统从自动SSN测量系统获得在静音I / O缓冲器和PLD上的每个切换I / O缓冲器之间的互感（例如，Mij）。该系统通过将互感乘以校正因子（例如，alphaj）来计算安静I / O缓冲器和每个开关I / O缓冲器之间的校正互感。该系统将每个校正的互感乘以流过开关I / O缓冲器的电流的比率，以获得由开关I / O缓冲器产生的感应电压。系统对PLD上所有开关I / O缓冲器的感应电压求和，以获得所有开关I / O缓冲器在静音I / O缓冲器中引起的总感应电压的估计。校正因子基于台架测量，并且取决于影响每个开关I / O缓冲器的同时开关噪声的幅度。

3. 发明授权

US08103469B1 Transceiver link bit error rate prediction 有权
标题翻译：收发器链路误码率预测
公开(公告)号：US08103469B1
公开(公告)日：2012-01-24
申请号：US11297611
申请日：2005-12-07
申请人： San Wong , Daniel Tun Lai Chow , Geping Liu
发明人： San Wong , Daniel Tun Lai Chow , Geping Liu
IPC分类号： G01R13/00 , G01R13/02 , G01R29/26
CPC分类号： G01R31/3171 , G01R31/31709
摘要： A method for predicting a predetermined bit error rate for an actual data transmission from a transmitter to a target receiver over an actual backplane link is disclosed. The method involves defining a simulated backplane corresponding to an actual backplane link intended to be used for data transmission between a transmitter and a target receiver. Once the simulated backplane is defined, a data transmission from the transmitter to the receiver is simulated and captured across the simulated backplane. A waveform simulation of the data transmission over the simulated backplane is then generated. The waveform simulation takes into account characteristics of the simulated backplane and the target receiver. From the waveform simulation, a total jitter for a predetermined bit error rate for the data transmission is extrapolated.
摘要翻译：公开了一种用于预测通过实际背板链路从发射机到目标接收机的实际数据传输的预定比特误码率的方法。该方法涉及定义对应于旨在用于发射机和目标接收机之间的数据传输的实际背板链路的模拟背板。一旦模拟背板被定义，从模拟背板模拟和捕获从发射机到接收机的数据传输。然后生成模拟背板上的数据传输的波形模拟。波形仿真考虑了仿真背板和目标接收机的特性。从波形模拟中，外推了用于数据传输的预定误码率的总抖动。

4. 发明授权

US08214781B1 Empirical prediction of simultaneous switching noise 有权
标题翻译：同步开关噪声的实证预测
公开(公告)号：US08214781B1
公开(公告)日：2012-07-03
申请号：US12208190
申请日：2008-09-10
申请人： Zhuyuan Liu , Geping Liu , San Wong
发明人： Zhuyuan Liu , Geping Liu , San Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5054 , G06F2217/82
摘要： In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., αj). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.
摘要翻译：在示例实施例中，系统从自动SSN测量系统获得在静音I / O缓冲器和PLD上的每个切换I / O缓冲器之间的互感（例如，Mij）。该系统通过将互感乘以校正因子（例如，αj）来计算安静I / O缓冲器和每个开关I / O缓冲器之间的校正互感。该系统将每个校正的互感乘以流过开关I / O缓冲器的电流的比率，以获得由开关I / O缓冲器产生的感应电压。系统对PLD上所有开关I / O缓冲器的感应电压求和，以获得所有开关I / O缓冲器在静音I / O缓冲器中引起的总感应电压的估计。校正因子基于台架测量，并且取决于影响每个开关I / O缓冲器的同时开关噪声的幅度。

5. 发明申请

US20120239338A1 EMPIRICAL PREDICTION OF SIMULTANEOUS SWITCHING NOISE 有权
标题翻译：同时切换噪声的实际预测
公开(公告)号：US20120239338A1
公开(公告)日：2012-09-20
申请号：US13484136
申请日：2012-05-30
申请人： Zhuyuan Liu , Geping Liu , San Wong
发明人： Zhuyuan Liu , Geping Liu , San Wong
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , G06F17/5054 , G06F2217/82
摘要： In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., αj). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.
摘要翻译：在示例实施例中，系统从自动SSN测量系统获得在静音I / O缓冲器和PLD上的每个切换I / O缓冲器之间的互感（例如，Mij）。该系统通过将互感乘以校正因子（例如，αj）来计算安静I / O缓冲器和每个开关I / O缓冲器之间的校正互感。该系统将每个校正的互感乘以流过开关I / O缓冲器的电流的比率，以获得由开关I / O缓冲器产生的感应电压。系统对PLD上所有开关I / O缓冲器的感应电压求和，以获得所有开关I / O缓冲器在静音I / O缓冲器中引起的总感应电压的估计。校正因子基于台架测量，并且取决于影响每个开关I / O缓冲器的同时开关噪声的幅度。

6. 发明申请

US20110125477A1 Inverse Modeling for Characteristic Prediction from Multi-Spectral and Hyper-Spectral Remote Sensed Datasets 审中-公开
标题翻译：用于多光谱和超光谱遥感数据集特征预测的逆建模
公开(公告)号：US20110125477A1
公开(公告)日：2011-05-26
申请号：US12780066
申请日：2010-05-14
申请人： Jonathan E. Lightner , Federico Valverde , Steven L. Wright , San Wong
发明人： Jonathan E. Lightner , Federico Valverde , Steven L. Wright , San Wong
IPC分类号： G06G7/48
CPC分类号： G05B13/048 , G05B17/02
摘要： Provided are methods and related devices for predicting the presence or level of one or more characteristics of a plant or plant population based on spectral, multi-spectral, or hyper-spectral data obtained by, e.g., remote sensing. The predictions and estimates furnished by the inventive methods and devices are useful in crop management, crop strategy, and optimization of agricultural production.
摘要翻译：提供了用于基于通过例如遥感获得的光谱，多光谱或超光谱数据来预测植物或植物群体的一个或多个特征的存在或水平的方法和相关装置。本发明方法和装置提供的预测和估计在作物管理，作物策略和农业生产优化中是有用的。

7. 发明授权

US08170823B1 Jitter estimation in phase-locked loops 有权
标题翻译：锁相环中的抖动估计
公开(公告)号：US08170823B1
公开(公告)日：2012-05-01
申请号：US13022886
申请日：2011-02-08
申请人： Daniel Tun Lai Chow , San Wong , Vincent K. Tsui , Lik Huay Lim , Man On Wong
发明人： Daniel Tun Lai Chow , San Wong , Vincent K. Tsui , Lik Huay Lim , Man On Wong
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , H03L7/07 , H03L7/08
摘要： A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.
摘要翻译：锁相环的特征在于分析其输出信号中的相位噪声，同时提供已知的输入相位噪声水平。得到的数据提供锁相环的内在相位噪声和增益。这些值提供了锁相环的输入相位噪声和输出相位噪声之间的一般关系，其允许估计对应于给定输入相位噪声水平的输出相位噪声，并且允许估计对应于给定电平的输入相位噪声的输出相位噪声。

8. 发明申请

US20090019304A1 METHOD AND APPARATUS FOR HARDWARE TIMING OPTIMIZER 有权
标题翻译：硬件时序优化器的方法与装置
公开(公告)号：US20090019304A1
公开(公告)日：2009-01-15
申请号：US12237385
申请日：2008-09-24
申请人： San Wong
发明人： San Wong
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G01R31/31919 , G01R31/31937 , G06F11/27 , G11C17/14 , G11C29/02 , G11C29/022 , G11C29/50012 , G11C2029/0401
摘要： A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.
摘要翻译：提供了一种用于优化通过可编程逻辑器件（PLD）在数据传输通道上发送的信号的信号操作参数的方法。生成发送测试模式，并且与用于通过数据传输信道发送和接收测试模式的一组信号操作参数相关联。数据传输通道从PLD的发送端口到接收端口循环。执行接收到的测试模式是否匹配发送测试模式的确定。记录匹配结果和信号操作参数集。通过PLD的处理器修改信号操作参数集合中的信号操作参数中的至少一个。根据修改的信号操作参数集合发送和接收另一个发送模式，并记录结果。包括用于优化数据传输到PLD的方法和相应的装置。

9. 发明授权

US07437591B1 Method and apparatus for hardware timing optimizer 有权
标题翻译：硬件定时优化器的方法和装置
公开(公告)号：US07437591B1
公开(公告)日：2008-10-14
申请号：US11039262
申请日：2005-01-18
申请人： San Wong
发明人： San Wong
IPC分类号： G06F1/04 , G06F1/00 , G11C11/00
CPC分类号： G06F1/04 , G01R31/31919 , G01R31/31937 , G06F11/27 , G11C17/14 , G11C29/02 , G11C29/022 , G11C29/50012 , G11C2029/0401
摘要： A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.
摘要翻译：提供了一种用于优化通过可编程逻辑器件（PLD）在数据传输通道上发送的信号的信号操作参数的方法。生成发送测试模式，并且与用于通过数据传输信道发送和接收测试模式的一组信号操作参数相关联。数据传输通道从PLD的发送端口到接收端口循环。执行接收到的测试模式是否匹配发送测试模式的确定。记录匹配结果和信号操作参数集。通过PLD的处理器修改信号操作参数集合中的信号操作参数中的至少一个。根据修改的信号操作参数集合发送和接收另一个发送模式，并记录结果。包括用于优化数据传输到PLD的方法和相应的装置。

10. 发明授权

US07890279B1 Jitter estimation in phase-locked loops 有权
标题翻译：锁相环中的抖动估计
公开(公告)号：US07890279B1
公开(公告)日：2011-02-15
申请号：US12189744
申请日：2008-08-11
申请人： Daniel Tun Lai Chow , San Wong , Vincent K. Tsui , Lik Huay Lim , Man On Wong
发明人： Daniel Tun Lai Chow , San Wong , Vincent K. Tsui , Lik Huay Lim , Man On Wong
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , H03L7/07 , H03L7/08
摘要： A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship between input phase noise and output phase noise for the phase-locked loop, which allows estimation of output phase noise corresponding to a given level of input phase noise, and allows estimation of input phase noise corresponding to a given level of output phase noise.
摘要翻译：锁相环的特征在于分析其输出信号中的相位噪声，同时提供已知的输入相位噪声电平。得到的数据提供锁相环的内在相位噪声和增益。这些值提供了锁相环的输入相位噪声和输出相位噪声之间的一般关系，其允许估计对应于给定输入相位噪声水平的输出相位噪声，并且允许估计对应于给定电平的输入相位噪声的输出相位噪声。

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