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1. 发明申请

US20050052817A1 CLAMPING AND DE-CLAMPING SEMICONDUCTOR WAFERS ON AN ELECTROSTATIC CHUCK USING WAFER INERTIAL CONFINEMENT BY APPLYING A SINGLE-PHASE SQUARE WAVE AC CLAMPING VOLTAGE 失效
标题翻译：通过应用单相波形交流钳位电压，使用波形器实时限制的静电卡盘上的钳位和去钳位半导体波形
公开(公告)号：US20050052817A1
公开(公告)日：2005-03-10
申请号：US10657449
申请日：2003-09-08
申请人： Peter Kellerman , Shu Qin , William DiVergilio
发明人： Peter Kellerman , Shu Qin , William DiVergilio
IPC分类号： H01L21/683 , H02N13/00 , H01H1/00
CPC分类号： H01L21/6833 , H02N13/00
摘要： The present invention is directed to a method for clamping a wafer to an electrostatic chuck using a single-phase square wave AC clamping voltage. The method comprises determining a single-phase square wave clamping voltage for the electrostatic chuck, wherein the determination is based, at least in part, on an inertial response time of the wafer. The wafer is placed on the electrostatic chuck, wherein a gap between the electrostatic chuck and the wafer is defined. The determined single-phase square wave clamping voltage is then applied, wherein the wafer is generally clamped to the electrostatic chuck within a predetermined distance, while an amount of electrostatic charge is generally not allowed to accumulate, thereby enabling a fast de-clamping of the wafer.
摘要翻译：本发明涉及使用单相方波交流钳位电压将晶片夹持到静电卡盘的方法。该方法包括确定用于静电卡盘的单相方波钳位电压，其中所述确定至少部分地基于晶片的惯性响应时间。将晶片放置在静电卡盘上，其中定义静电卡盘和晶片之间的间隙。然后施加确定的单相方波钳位电压，其中晶片通常在预定距离内被夹持在静电卡盘上，而静电电荷的量通常不允许累积，从而能够快速地去夹紧晶圆。

2. 发明申请

US20050099758A1 METHOD OF MAKING A MEMS ELECTROSTATIC CHUCK 失效
标题翻译：制造MEMS静电卡盘的方法
公开(公告)号：US20050099758A1
公开(公告)日：2005-05-12
申请号：US10695153
申请日：2003-10-28
申请人： Peter Kellerman , Shu Qin , Ernie Allen , Douglas Brown
发明人： Peter Kellerman , Shu Qin , Ernie Allen , Douglas Brown
IPC分类号： H01L21/683 , H02B1/00
CPC分类号： H01L21/6833
摘要： The present invention is directed to a method of forming a clamping plate for a multi-polar electrostatic chuck. The method comprises forming a first electrically conductive layer over a semiconductor platform and defining a plurality of portions of the first electrically conductive layer which are electrically isolated from one another. A first electrically insulative layer is formed over the first electrically conductive layer, the first electrically insulative layer comprising a top surface having a plurality of MEMS protrusions extending a first distance therefrom. A plurality of poles are furthermore electrically connected to the respective plurality of portions of the first electrically conductive layer, wherein a voltage applied between the plurality of poles is operable to induce an electrostatic force in the clamping plate.
摘要翻译：本发明涉及一种形成多极静电卡盘夹紧板的方法。该方法包括在半导体平台上形成第一导电层，并且限定彼此电隔离的第一导电层的多个部分。第一电绝缘层形成在第一导电层之上，第一电绝缘层包括具有从其延伸第一距离的多个MEMS突起的顶表面。多个极还电连接到第一导电层的相应多个部分，其中施加在多个极之间的电压可操作以在夹持板中引起静电力。

3. 发明申请

US20050079737A1 MEMS BASED CONTACT CONDUCTIVITY ELECTROSTATIC CHUCK 失效
标题翻译：基于MEMS的接触电导率静电卡盘
公开(公告)号：US20050079737A1
公开(公告)日：2005-04-14
申请号：US10683679
申请日：2003-10-10
申请人： Peter Kellerman , Shu Qin , Ernie Allen , Douglas Brown
发明人： Peter Kellerman , Shu Qin , Ernie Allen , Douglas Brown
IPC分类号： H01L21/683 , H01L21/66
CPC分类号： H01L21/6831 , Y10S438/964
摘要： The present invention is directed to a method for clamping and processing a semiconductor substrate using a semiconductor processing apparatus. According to one aspect of the present invention, a multi-polar electrostatic chuck and associated method is disclosed which provides heating or cooling of a substrate by thermal contact conduction between the electrostatic chuck and the substrate. The multi-polar electrostatic chuck includes a semiconductor platform having a plurality of protrusions that define gaps therebetween, wherein a surface roughness of the plurality of protrusions is less than 100 Angstroms. The electrostatic chuck further includes a voltage control system operable to control a voltage applied to the electrostatic chuck to thus control a contact heat transfer coefficient of the electrostatic chuck, wherein the heat transfer coefficient of the electrostatic chuck is primarily a function of a contact pressure between the substrate and the plurality of protrusions.
摘要翻译：本发明涉及使用半导体处理装置夹持和处理半导体衬底的方法。根据本发明的一个方面，公开了一种多极静电卡盘和相关方法，其通过静电卡盘和基板之间的热接触传导来提供加热或冷却基板。多极静电卡盘包括具有多个突起的半导体平台，所述突起在其间形成间隙，其中多个突起的表面粗糙度小于100埃。静电卡盘还包括电压控制系统，其可操作以控制施加到静电卡盘的电压，从而控制静电卡盘的接触传热系数，其中静电卡盘的传热系数主要是介于静电卡盘之间的接触压力的函数基板和多个突起。

4. 发明申请

US20050057881A1 Clamping and de-clamping semiconductor wafers on a J-R electrostatic chuck having a micromachined surface by using force delay in applying a single-phase square wave AC clamping voltage 有权
标题翻译：在具有微加工表面的J-R静电卡盘上夹紧和去夹紧半导体晶片，通过在施加单相方波交流钳位电压时使用力延迟
公开(公告)号：US20050057881A1
公开(公告)日：2005-03-17
申请号：US10661180
申请日：2003-09-12
申请人： Shu Qin , Peter Kellerman
发明人： Shu Qin , Peter Kellerman
IPC分类号： H01L21/683 , H01H1/00 , H02B1/00
CPC分类号： H01L21/6833
摘要： The present invention is directed to a method and a system for clamping a wafer to a J-R electrostatic chuck using a single-phase square wave AC clamping voltage. The method comprises determining a single-phase square wave clamping voltage for the J-R electrostatic chuck, wherein the determination is based, at least in part, on a minimum residual clamping force associated with the wafer and the electrostatic chuck and a surface topography of a leaky dielectric layer associated therewith. The wafer is placed on the electrostatic chuck; and the determined clamping voltage is applied to the electrostatic chuck, therein electrostatically clamping the wafer to the electrostatic chuck, wherein at least the minimum residual clamping force is maintained during a polarity switch of the single-phase square wave clamping voltage. The determination of the surface topography comprises a first gap and a second gap between the wafer and the electrostatic chuck and an island area ratio, wherein a difference in RC time constants associated with the respective first gap and second gap is provided such that at least the minimum residual clamping force is maintained during the polarity switch. Upon removal of the square wave clamping voltage, the de-clamping time is substantially reduced, and corresponds to the pulse width of the square wave clamping voltage.
摘要翻译：本发明涉及一种使用单相方波交流钳位电压将晶片夹持到J-R静电卡盘的方法和系统。该方法包括确定用于JR静电卡盘的单相方波钳位电压，其中所述确定至少部分地基于与晶片和静电卡盘相关联的最小剩余夹持力和泄漏的表面形貌与之相关的电介质层。将晶片放置在静电卡盘上; 并且将确定的钳位电压施加到静电卡盘，其中将晶片静电夹持到静电卡盘，其中在单相方波钳位电压的极性开关期间至少保持最小的剩余钳位力。表面形貌的确定包括晶片和静电卡盘之间的第一间隙和第二间隙以及岛面积比，其中提供与相应的第一间隙和第二间隙相关联的RC时间常数的差异，使得至少在极性开关期间维持最小的剩余夹紧力。在去除方波钳位电压时，去夹紧时间大大降低，并且对应于方波钳位电压的脉冲宽度。

5. 发明申请

US20130089966A1 Methods of Processing Units Comprising Crystalline Materials, and Methods of Forming Semiconductor-On-Insulator Constructions 有权
标题翻译：包含结晶材料的加工单元的方法以及形成半导体绝缘体结构的方法
公开(公告)号：US20130089966A1
公开(公告)日：2013-04-11
申请号：US13267522
申请日：2011-10-06
申请人： Shu Qin , Ming Zhang
发明人： Shu Qin , Ming Zhang
IPC分类号： H01L21/263
CPC分类号： H01L21/68735 , H01L21/6831 , H01L21/76254
摘要： Some embodiments include methods of processing a unit containing crystalline material. A damage region may be formed within the crystalline material, and a portion of the unit may be above the damage region. A chuck may be used to bend the unit and thereby induce cleavage along the damage region to form a structure from the portion of the unit above the damage region. Some embodiments include methods of forming semiconductor-on-insulator constructions. A unit may be formed to have dielectric material over monocrystalline semiconductor material. A damage region may be formed within the monocrystalline semiconductor material, and a portion of the monocrystalline semiconductor material may be between the damage region and the dielectric material. The unit may be incorporated into an assembly with a handle component, and a chuck may be used to contort the assembly and thereby induce cleavage along the damage region.
摘要翻译：一些实施方案包括处理含有结晶材料的单元的方法。可以在结晶材料内形成损伤区域，并且该单元的一部分可能在损伤区域之上。可以使用卡盘来弯曲单元，从而沿着损伤区域引起切割，以从损伤区域上方的单元部分形成结构。一些实施例包括形成绝缘体上半导体结构的方法。单元可以形成为具有超过单晶半导体材料的电介质材料。可以在单晶半导体材料内形成损伤区域，并且单晶半导体材料的一部分可以在损伤区域和电介质材料之间。该单元可以结合到具有把手部件的组件中，并且卡盘可以用于扭曲组件，从而引起沿着损伤区域的切割。

6. 发明授权

US07737010B2 Method of photoresist strip for plasma doping process of semiconductor manufacturing 有权
标题翻译：半导体制造等离子体掺杂工艺的光刻胶条的方法
公开(公告)号：US07737010B2
公开(公告)日：2010-06-15
申请号：US11404306
申请日：2006-04-14
申请人： Shu Qin , Allen McTeer , Robert J. Hanson
发明人： Shu Qin , Allen McTeer , Robert J. Hanson
IPC分类号： H01L21/26
CPC分类号： H01L21/2236 , H01L21/31133 , H01L21/31138 , H01L29/78
摘要： A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the semiconductor substrate, implanting a dopant into the semiconductor substrate, and removing a dopant-containing layer from the photoresist layer. The dopant-containing layer includes dopant residuals and a carbon-rich crust and may be formed during implantation. The dopant-containing layer may be removed from the photoresist layer by exposing the dopant-containing layer to a water rinse, a chlorinated plasma or to a fluorinated plasma. The water rinse may include deionized water that is maintained at a temperature that ranges from approximately 25° C. to approximately 80° C. The fluorinated plasma may be formed from a gaseous precursor selected from the group consisting of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, sulfur hexafluoride, and mixtures thereof. A method of forming an ultrashallow junction is also disclosed.
摘要翻译：公开了一种形成中间半导体器件的方法，其包括提供半导体衬底，在半导体衬底上形成光致抗蚀剂层，将掺杂剂注入到半导体衬底中，以及从光刻胶层去除掺杂剂层。含掺杂剂层包括掺杂剂残留物和富含碳的地壳，并且可以在植入期间形成。通过将含掺杂剂的层暴露于水漂洗，氯化等离子体或氟化等离子体，可以从光致抗蚀剂层中除去含掺杂物层。水冲洗可以包括保持在约25℃至约80℃范围内的温度的去离子水。氟化等离子体可以由选自三氟化氮，四氟化碳，三氟甲烷六氟乙烷，六氟化硫及其混合物。还公开了形成超短接头的方法。

7. 发明授权

US07476556B2 Systems and methods for plasma processing of microfeature workpieces 有权
标题翻译：微型工件等离子体处理的系统和方法
公开(公告)号：US07476556B2
公开(公告)日：2009-01-13
申请号：US11201668
申请日：2005-08-11
申请人： Shu Qin , Allen McTeer
发明人： Shu Qin , Allen McTeer
IPC分类号： H01L21/66 , H01L21/00
CPC分类号： H01J37/32917 , C23C14/54 , C23C16/52 , G01N21/73 , H01J37/32935 , H01J37/32972
摘要： Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.
摘要翻译：本文公开了微型工件的等离子体处理的系统和方法。在一个实施例中，一种方法包括在微型工件位于腔室中的同时在腔室中产生等离子体，测量等离子体的光发射，以及基于所测量的光发射来确定等离子体的参数。该参数可以是等离子体的离子密度或其他参数。

8. 发明申请

US20070284686A1 Method of forming elevated photosensor and resulting structure 有权
标题翻译：形成升高的光电传感器和结果的方法
公开(公告)号：US20070284686A1
公开(公告)日：2007-12-13
申请号：US11449743
申请日：2006-06-09
申请人： Saijin Liu , Shu Qin
发明人： Saijin Liu , Shu Qin
IPC分类号： H01L31/0232
CPC分类号： H01L27/14634 , H01L21/76254 , H01L27/1469
摘要： Elevated crystal silicon photosensors for imagers pixels, each photosensor formed of crystal silicon above the surface of a substrate that has pixel circuitry formed thereon. The imager has a high fill factor and good imaging properties due to the crystal silicon photosensor.
摘要翻译：用于成像器像素的升高的晶体硅光电传感器，每个光电传感器由其上形成有像素电路的衬底表面上的晶体硅形成。由于晶体硅光电传感器，成像器具有高填充因子和良好的成像性能。

9. 发明申请

US20070243700A1 Method of photoresist strip for plasma doping process of semiconductor manufacturing 有权
标题翻译：半导体制造等离子体掺杂工艺的光刻胶条的方法
公开(公告)号：US20070243700A1
公开(公告)日：2007-10-18
申请号：US11404306
申请日：2006-04-14
申请人： Shu Qin , Allen McTeer , Robert Hanson
发明人： Shu Qin , Allen McTeer , Robert Hanson
IPC分类号： H01L21/426
CPC分类号： H01L21/2236 , H01L21/31133 , H01L21/31138 , H01L29/78
摘要： A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the semiconductor substrate, implanting a dopant into the semiconductor substrate, and removing a dopant-containing layer from the photoresist layer. The dopant-containing layer includes dopant residuals and a carbon-rich crust and may be formed during implantation. The dopant-containing layer may be removed from the photoresist layer by exposing the dopant-containing layer to a water rinse, a chlorinated plasma or to a fluorinated plasma. The water rinse may include deionized water that is maintained at a temperature that ranges from approximately 25° C. to approximately 80° C. The fluorinated plasma may be formed from a gaseous precursor selected from the group consisting of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, sulfur hexafluoride, and mixtures thereof. A method of forming an ultrashallow junction is also disclosed.
摘要翻译：公开了一种形成中间半导体器件的方法，其包括提供半导体衬底，在半导体衬底上形成光致抗蚀剂层，将掺杂剂注入到半导体衬底中，以及从光刻胶层去除掺杂剂层。含掺杂剂层包括掺杂剂残留物和富含碳的地壳，并且可以在植入期间形成。通过将含掺杂剂的层暴露于水漂洗，氯化等离子体或氟化等离子体，可以从光致抗蚀剂层中除去含掺杂物层。水冲洗可以包括保持在约25℃至约80℃范围内的温度的去离子水。氟化等离子体可以由选自三氟化氮，四氟化碳，三氟甲烷六氟乙烷，六氟化硫及其混合物。还公开了形成超短接头的方法。

10. 发明授权

US07072166B2 Clamping and de-clamping semiconductor wafers on a J-R electrostatic chuck having a micromachined surface by using force delay in applying a single-phase square wave AC clamping voltage 有权
标题翻译：在具有微加工表面的J-R静电卡盘上夹紧和去夹紧半导体晶片，通过在施加单相方波交流钳位电压时使用力延迟
公开(公告)号：US07072166B2
公开(公告)日：2006-07-04
申请号：US10661180
申请日：2003-09-12
申请人： Shu Qin , Peter L. Kellerman
发明人： Shu Qin , Peter L. Kellerman
IPC分类号： H01H1/00
CPC分类号： H01L21/6833
摘要： The present invention is directed to a method and a system for clamping a wafer to a J-R electrostatic chuck using a single-phase square wave AC clamping voltage. The method comprises determining a single-phase square wave clamping voltage for the J-R electrostatic chuck, wherein the determination is based, at least in part, on a minimum residual clamping force associated with the wafer and the electrostatic chuck and a surface topography of a leaky dielectric layer associated therewith. The wafer is placed on the electrostatic chuck; and the determined clamping voltage is applied to the electrostatic chuck, therein electrostatically clamping the wafer to the electrostatic chuck, wherein at least the minimum residual clamping force is maintained during a polarity switch of the single-phase square wave clamping voltage. The determination of the surface topography comprises a first gap and a second gap between the wafer and the electrostatic chuck and an island area ratio, wherein a difference in RC time constants associated with the respective first gap and second gap is provided such that at least the minimum residual clamping force is maintained during the polarity switch. Upon removal of the square wave clamping voltage, the de-clamping time is substantially reduced, and corresponds to the pulse width of the square wave clamping voltage.
摘要翻译：本发明涉及一种使用单相方波交流钳位电压将晶片夹持到J-R静电卡盘的方法和系统。该方法包括确定用于JR静电卡盘的单相方波钳位电压，其中所述确定至少部分地基于与晶片和静电卡盘相关联的最小剩余夹持力和泄漏的表面形貌与之相关的电介质层。将晶片放置在静电卡盘上; 并且将确定的钳位电压施加到静电卡盘，其中将晶片静电夹持到静电卡盘，其中在单相方波钳位电压的极性开关期间至少保持最小的剩余钳位力。表面形貌的确定包括晶片和静电卡盘之间的第一间隙和第二间隙以及岛面积比，其中提供与相应的第一间隙和第二间隙相关联的RC时间常数的差异，使得至少在极性开关期间维持最小的剩余夹紧力。在去除方波钳位电压时，去夹紧时间大大降低，并且对应于方波钳位电压的脉冲宽度。

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