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1. 发明授权

US09154117B2 Pulse generation in dual supply systems 有权
标题翻译：双电源系统中的脉冲发生
公开(公告)号：US09154117B2
公开(公告)日：2015-10-06
申请号：US13787530
申请日：2013-03-06
申请人： QUALCOMM Incorporated
发明人： Changho Jung , Nishith Desai , Rakesh Vattikonda
IPC分类号： H03K3/00 , H03K3/356
CPC分类号： H03K3/356104
摘要： Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.
摘要翻译：公开了各种装置和方法。该系统描述了脉冲发生器，其包括被配置为由第一电压供电的第一级; 以及第二级，其被配置为由不同于所述第一电压的第二电压供电，其中所述第二级还被配置为响应于包括来自所述第二级的触发和来自所述第一级的输入而产生脉冲。

2. 发明授权

US08934278B2 Hybrid ternary content addressable memory 有权
标题翻译：混合三元内容可寻址内存
公开(公告)号：US08934278B2
公开(公告)日：2015-01-13
申请号：US13730487
申请日：2012-12-28
申请人： QUALCOMM Incorporated
发明人： Rakesh Vattikonda , Nishith Desai , ChangHo Jung , Sei Seung Yoon , Esin Terzioglu
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.
摘要翻译：混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。第一个TCAM阶段与第二个TCAM阶段不同。

3. 发明申请

US20140219039A1 WRITE DRIVER FOR WRITE ASSISTANCE IN MEMORY DEVICE 有权
标题翻译：用于存储器件中的写入辅助的写驱动器
公开(公告)号：US20140219039A1
公开(公告)日：2014-08-07
申请号：US13760988
申请日：2013-02-06
申请人： QUALCOMM INCORPORATED
发明人： Changho Jung , Nishith Desai , Rakesh Vattikonda
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C5/14 , G11C7/00 , G11C8/08 , G11C11/4085 , G11C11/419
摘要： A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP≧VddM>VddMlower.
摘要翻译：提供一种写辅助驱动器电路，即使当电源电压降低时，也可以在写入操作中帮助存储器单元（例如，易失性存储器位单元）来保持存储器核心处的电压足够高以用于正确的写入操作。写辅助驱动器电路可以被配置为在待机操作模式期间向位单元核提供存储器电源电压VddM。在写入操作模式中，写入辅助驱动器电路可以向位单元核心以及本地写入位线（lwbl）和本地写入位线条（lwblb）中的至少一个提供降低的存储器电源电压VddMlower。此外，写辅助驱动器电路还可以向本地写入字线（lww1）提供外围电源电压VddP，其中VddP≥VddM> VddMlower。

4. 发明申请

US20150029782A1 WIDE RANGE MULTIPORT BITCELL 有权
标题翻译：宽范围多点比特
公开(公告)号：US20150029782A1
公开(公告)日：2015-01-29
申请号：US13953473
申请日：2013-07-29
申请人： QUALCOMM Incorporated
发明人： Changho Jung , Rakesh Vattikonda , Nishith Desai , Sei Seung Yoon
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16
摘要： A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.
摘要翻译：包括一对交叉耦合的反相器的多端口位单元通过在写入操作期间从电源和接地中选择性隔离交叉耦合的反相器中的第一个而提供增加的写入速度和增强的工作电压范围。写入操作通过写入端口发生，该写入端口包括被配置为将由第一交叉耦合的反相器驱动的第一节点耦合到写入位线的传输门极。位单元中的剩余的第二交叉耦合反相器被配置为驱动耦合到多个读端口的第二节点。

5. 发明申请

US20140185348A1 HYBRID TERNARY CONTENT ADDRESSABLE MEMORY 有权
标题翻译：混合内容可寻址记忆
公开(公告)号：US20140185348A1
公开(公告)日：2014-07-03
申请号：US13730487
申请日：2012-12-28
申请人： QUALCOMM INCORPORATED
发明人： Rakesh Vattikonda , Nishith Desai , ChangHo Jung , Sei Seung Yoon , Esin Terzioglu
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.
摘要翻译：混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。第一个TCAM阶段与第二个TCAM阶段不同。

6. 发明申请

US20140177310A1 PSEUDO-NOR CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY 有权
标题翻译：用于三次内容可寻址存储器的PSEUDO-NORCELL
公开(公告)号：US20140177310A1
公开(公告)日：2014-06-26
申请号：US13727494
申请日：2012-12-26
申请人： QUALCOMM INCORPORATED
发明人： Rakesh Vattikonda , Nishith Desai , ChangHo Jung
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match.
摘要翻译：三元内容可寻址存储器（TCAM）内的方法包括从当前TCAM级的上拉晶体管的栅极处和当前TCAM的下拉晶体管的栅极处接收来自先前TCAM级的匹配线输出阶段。当从前一个TCAM级输出的匹配线指示不匹配时，该方法通过下拉晶体管将当前TCAM级的匹配线条设置为低值。当从前一个TCAM级输出的匹配线指示匹配时，该方法还通过上拉晶体管将当前TCAM级的匹配线条设置为高值。

7. 发明授权

US09948303B2 High speed voltage level shifter 有权
公开(公告)号：US09948303B2
公开(公告)日：2018-04-17
申请号：US15367751
申请日：2016-12-02
申请人： QUALCOMM Incorporated
发明人： Venkat Narayanan , Rakesh Vattikonda , De Lu , Ramaprasath Vilangudipitchai , Samrat Sinharoy , Rui Chen
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/00
CPC分类号： H03K19/018521 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/01855 , H03K19/0963
摘要： In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

8. 发明授权

US09941866B2 Apparatus for design for testability of multiport register arrays 有权
公开(公告)号：US09941866B2
公开(公告)日：2018-04-10
申请号：US15207800
申请日：2016-07-12
申请人： QUALCOMM Incorporated
发明人： Rakesh Vattikonda , Samrat Sinharoy , De Lu
IPC分类号： H03K3/289 , H03K3/037 , G01R31/317 , G01R31/3185
CPC分类号： H03K3/0372 , G01R31/31704 , G01R31/31723 , G01R31/318541
摘要： In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

9. 发明授权

US09859893B1 High speed voltage level shifter 有权
公开(公告)号：US09859893B1
公开(公告)日：2018-01-02
申请号：US15367706
申请日：2016-12-02
申请人： QUALCOMM Incorporated
发明人： Venkat Narayanan , Rakesh Vattikonda , De Lu , Ramaprasath Vilangudipitchai , Samrat Sinharoy , Rui Chen
IPC分类号： H03K3/35 , H03K19/00 , G09G3/20 , H03K19/0185 , H03K3/356
CPC分类号： H03K19/018521 , H03K3/012 , H03K3/356113 , H03K3/35613 , H03K3/356182 , H03K19/0013
摘要： In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

10. 发明申请

US20150310901A1 MEMORY WITH A SLEEP MODE 审中-公开
标题翻译：具有睡眠模式的记忆
公开(公告)号：US20150310901A1
公开(公告)日：2015-10-29
申请号：US14261192
申请日：2014-04-24
申请人： QUALCOMM INCORPORATED
发明人： Changho Jung , Rakesh Vattikonda , Tony Chung Yiu Kwok
IPC分类号： G11C7/12 , G11C5/14
CPC分类号： G11C7/12 , G11C5/148 , G11C7/18 , G11C8/16 , G11C11/417
摘要： A memory and a method for operating the memory having a sleep mode are provided. The memory one or more storage elements and a bitline coupled to the one or more storage elements. A precharge circuit is configured to precharge the bitline during a precharge period and float the bitline during a sleep mode. An operating circuit coupled to the one or more storage elements, wherein at least one of the operating circuit and the one or more storage elements being configured to remain electrically coupled to a supply voltage in the sleep mode.
摘要翻译：提供了一种用于操作具有休眠模式的存储器的存储器和方法。存储器一个或多个存储元件和耦合到一个或多个存储元件的位线。预充电电路被配置为在预充电周期期间预充电位线，并且在睡眠模式期间浮动位线。耦合到所述一个或多个存储元件的操作电路，其中所述操作电路和所述一个或多个存储元件中的至少一个被配置为在睡眠模式下保持电耦合到电源电压。

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