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1. 发明申请

US20080285549A1 SYNCHRONOUS READ CHANNEL 失效
标题翻译：同步读通道
公开(公告)号：US20080285549A1
公开(公告)日：2008-11-20
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

2. 发明授权

US5978162A Synchronous read channel integrated circuit employing a channel quality circuit for calibration 失效
标题翻译：采用通道质量电路进行校准的同步读通道集成电路
公开(公告)号：US5978162A
公开(公告)日：1999-11-02
申请号：US821174
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。通道质量电路积累由读通道产生的各种信号，例如采样误差，增益误差，定时误差等，用于校准读通道分量并估计误码率。

3. 发明授权

US5966257A Synchronous read channel integrated circuit employing discrete time timing recovery 失效
标题翻译：采用离散时间定时恢复的同步读通道集成电路
公开(公告)号：US5966257A
公开(公告)日：1999-10-12
申请号：US821011
申请日：1997-03-19
申请人： Richard T. Behrens , Alan J. Armstrong , Trent Dudley , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Alan J. Armstrong , Trent Dudley , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a partial response of the form (1-D)(1+D).sup.n where n>1, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据形式（1-D）（1 + D）n的部分响应滤波样本值，其中n> 1，从滤波的采样值中提取定时信息，并使用离散时间序列检测器从滤波的采样值中检测估计数据序列。

4. 发明授权

US5424881A Synchronous read channel 失效
公开(公告)号：US5424881A
公开(公告)日：1995-06-13
申请号：US12266
申请日：1993-02-01
申请人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
发明人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , G06F11/10 , G11B20/16
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

5. 发明授权

US07957370B2 Synchronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US07957370B2
公开(公告)日：2011-06-07
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

6. 发明授权

US5844509A Synchronous read channel employing a data randomizer 失效
标题翻译：采用数据随机化器的同步读通道
公开(公告)号：US5844509A
公开(公告)日：1998-12-01
申请号：US820926
申请日：1997-03-19
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , H03M7/46
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation. When the Data Randomizer is enabled, the probability of encountering any specific pattern of length n channel bits at a randomly selected location within encoded data is approximately 1/2.sup.n.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。读通道采用数据随机化器，其处理未编码的用户数据，以确保具有最坏情况模式灵敏度的信道位模式不会比从随机用户数据预期的更频繁地发生。数据随机化器采用两个线性反馈移位寄存器：一个产生一个63位的序列，它与每对数据位的MSB相对而言是EXLUSIVE-OR-，另一个产生一个127位的序列，它是独占每对数据位的LSB。 Data Randomizer不影响错误传播。当启用数据随机器时，在编码数据内随机选择的位置遇到长度为n个通道位的任何特定模式的概率大约为+ E，fra 1/2 + EE n。

7. 发明授权

US5297184A Gain control circuit for synchronous waveform sampling 失效
标题翻译：用于同步波形采样的增益控制电路
公开(公告)号：US5297184A
公开(公告)日：1994-03-22
申请号：US12049
申请日：1993-02-01
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , H03G3/20 , H04L27/08
CPC分类号： H03G3/001 , G11B20/10009 , H03G3/3036
摘要： A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.
摘要翻译：一种混合的模拟和数字增益控制电路，用于控制模拟输入信号的幅度。该电路具有可变增益放大器，其接收来自读/写记录头前置放大器的信号。可变增益放大器的输出通过多路复用器和均衡器连接到模数转换器，用于在受控采样时将模拟信号转换为数字采样值。增益控制电路接收指示何时发生脉冲的数字值和脉冲检测器的输出。增益控制电路内的增益误差检测器确定每个检测脉冲幅度的误差量，并将该误差量滤波并通过数模转换器发送，然后通过取幂电路。指数电路的输出连接到可变增益放大器的增益控制输入。

8. 发明授权

US5917668A Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
标题翻译：采用频率合成器的同步读通道，用于将定时恢复锁相环锁定到参考频率
公开(公告)号：US5917668A
公开(公告)日：1999-06-29
申请号：US822174
申请日：1997-03-21
申请人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
发明人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。为了在进入定时恢复采集模式时确保小的频率误差，定时恢复锁相环（PLL）首先被锁定到与写入频率相同的标称读取频率。这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。此后，来自读取头的模拟信号被多路复用到定时恢复PLL中，以便获取在用户数据之前记录的获取前导码的实际频率和相位。

9. 发明授权

US5844738A Synchronous read channel employing a sequence detector with programmable detector levels 失效
标题翻译：采用具有可编程检测器电平的序列检测器的同步读通道
公开(公告)号：US5844738A
公开(公告)日：1998-12-01
申请号：US821175
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列从使用与部分响应匹配的格子型序列检测器的滤波样本值。网格序列检测器包括可编程检测器级别，其允许在将序列检测器与部分响应匹配时具有最大的灵活性。

10. 发明授权

US6021011A Synchronous read channel employing a digital center frequency setting for a variable frequency oscillator in discrete time timing recovery 失效
标题翻译：在离散时间定时恢复中采用可变频率振荡器的数字中心频率设置的同步读取通道
公开(公告)号：US6021011A
公开(公告)日：2000-02-01
申请号：US822603
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。读通道内的离散时间定时恢复包括用于产生采样时钟的可变频率振荡器（VFO）。 VFO的中心工作频率通过存储数字中心频率设置的可编程寄存器进行调整。从采样值计算相位误差，并与中心频率设置相结合，以控制VFO输出端采样时钟的频率和相位。

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