专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6157657A System and method for data bus interface 失效
标题翻译：数据总线接口的系统和方法
公开(公告)号：US6157657A
公开(公告)日：2000-12-05
申请号：US944624
申请日：1997-10-02
申请人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
发明人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
IPC分类号： H04L12/56 , H04L12/64 , H04Q11/04 , H04J3/24
CPC分类号： H04L49/3081 , H04L12/6402 , H04L49/30 , H04L49/552 , H04Q11/0478 , H04J2203/0048 , H04J2203/0089 , H04L2012/5615 , H04L2012/5652 , H04L2012/5672 , H04L49/3009
摘要： A system for interfacing with a data bus is provided. The system includes an egress bus data interface that can receive a single incoming stream of STM data and ATM data. The egress bus data interface transmits a single incoming stream of STM data, and a single incoming stream of ATM. The system also includes an ingress bus data interface. The ingress bus interface receives a single outgoing stream of STM data and a single outgoing stream of ATM data. The STM data and ATM data are transmitted in a single outgoing stream.
摘要翻译：提供了一种与数据总线接口的系统。该系统包括可以接收STM数据和ATM数据的单个输入流的出口总线数据接口。出口总线数据接口传输单个进入的STM数据流，以及单个进入的ATM流。该系统还包括一个入口总线数据接口。入口总线接口接收STM数据的单个输出流和ATM数据的单个输出流。 STM数据和ATM数据在单个输出流中传输。

2. 发明授权

US06320877B1 System and method for data bus interface 有权
标题翻译：数据总线接口的系统和方法
公开(公告)号：US06320877B1
公开(公告)日：2001-11-20
申请号：US09522661
申请日：2000-03-10
申请人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
发明人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
IPC分类号： H04J324
CPC分类号： H04L49/3081 , H04J2203/0048 , H04J2203/0089 , H04L12/6402 , H04L49/30 , H04L49/3009 , H04L49/552 , H04L2012/5615 , H04L2012/5652 , H04L2012/5672 , H04Q11/0478
摘要： A system for interfacing with a data bus is provided. The system includes an egress bus data interface that can receive a single incoming stream of STM data and ATM data. The egress bus data interface transmits a single incoming stream of STM data, and a single incoming stream of ATM. The system also includes an ingress bus data interface. The ingress bus interface receives a single outgoing stream of STM data and a single outgoing stream of ATM data. The STM data and ATM data are transmitted in a single outgoing stream.
摘要翻译：提供了一种与数据总线接口的系统。该系统包括可以接收STM数据和ATM数据的单个输入流的出口总线数据接口。出口总线数据接口传输单个进入的STM数据流，以及单个进入的ATM流。该系统还包括一个入口总线数据接口。入口总线接口接收STM数据的单个输出流和ATM数据的单个输出流。 STM数据和ATM数据在单个输出流中传输。

3. 发明授权

US06246681B1 System and method for plane selection 失效
标题翻译：平面选择的系统和方法
公开(公告)号：US06246681B1
公开(公告)日：2001-06-12
申请号：US08994315
申请日：1997-12-19
申请人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
发明人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
IPC分类号： H04L1266
CPC分类号： H04L49/153 , H04L12/6402 , H04L2012/5613 , H04L2012/5627 , H04Q11/0478
摘要： A system for selecting one of two or more parallel planes of data is provided. The system includes a first data buffer that is connected to a first data bus that carries a stream of datagrams. The first data buffer receives and stores datagrams from the first data bus. The system also includes a second data buffer that is connected to a second data bus that carries a stream of datagrams. The second data buffer receives and stores datagrams from the second data bus. A selection controller connected to the first data buffer and the second data buffer analyzes the datagrams stored in the first and second data buffers, and selects one of the datagrams to be the primary datagram.
摘要翻译：提供了用于选择两个或更多个平行数据平面中的一个的系统。该系统包括连接到第一数据总线的第一数据缓冲器，该数据总线承载数据报流。第一数据缓冲器接收并存储来自第一数据总线的数据报。该系统还包括第二数据缓冲器，其连接到携带数据流流的第二数据总线。第二数据缓冲器接收并存储来自第二数据总线的数据报。连接到第一数据缓冲器和第二数据缓冲器的选择控制器分析存储在第一和第二数据缓冲器中的数据报，并选择数据报中的一个作为主数据报。

4. 发明授权

US5959987A System and apparatus for data bus interface 失效
标题翻译：数据总线接口的系统和设备
公开(公告)号：US5959987A
公开(公告)日：1999-09-28
申请号：US944623
申请日：1997-10-02
申请人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
发明人： Russell L. Humphrey , Jose A. Garcia , Long V. Vo
IPC分类号： H04L12/56 , H04L12/64 , H04Q11/04 , H04L12/66
CPC分类号： H04Q11/0478 , H04L12/6402 , H04L49/102 , H04L49/3081 , H04J2203/0048 , H04J2203/0089 , H04L2012/5615 , H04L2012/5652 , H04L2012/5672
摘要： A data bus interface circuit is provided. The data bus interface circuit includes interface circuitry that can receive, store, and transmit data. Egress bus input circuitry is connected to the interface circuitry. The egress bus input circuitry receives incoming STM and ATM data from a first egress data bus. STM egress bus input circuitry is connected to the interface circuitry. The STM egress bus input circuitry transmits the incoming STM data over a second egress data bus. ATM egress bus input circuitry connected to the interface circuitry transmits the incoming ATM data over a third egress data bus. STM ingress bus input circuitry receives outgoing synchronous transfer mode data, and ATM ingress bus input circuitry receives outgoing asynchronous transfer mode data. Ingress bus output circuitry connected to the interface circuitry transmits outgoing STM and outgoing ATM data over a third ingress data bus.
摘要翻译：提供数据总线接口电路。数据总线接口电路包括可以接收，存储和发送数据的接口电路。出口总线输入电路连接到接口电路。出口总线输入电路从第一出口数据总线接收输入的STM和ATM数据。 STM出口总线输入电路连接到接口电路。 STM出口总线输入电路通过第二个出口数据总线传输输入的STM数据。连接到接口电路的ATM出口总线输入电路通过第三出口数据总线传输输入的ATM数据。 STM入口总线输入电路接收输出同步传输模式数据，ATM入口总线输入电路接收输出异步传输模式数据。连接到接口电路的入口总线输出电路通过第三个入口数据总线传送输出STM和输出的ATM数据。

5. 发明授权

US06285673B1 OC3 delivery unit; bus control module 失效
标题翻译： OC3送货单位; 总线控制模块
公开(公告)号：US06285673B1
公开(公告)日：2001-09-04
申请号：US09052694
申请日：1998-03-31
申请人： Bracey J. Blackburn , Robert S. Gammenthaler, Jr. , Donald B. Hay , Thomas E. Cooper , Serge F. Fourcand , Long V. Vo
发明人： Bracey J. Blackburn , Robert S. Gammenthaler, Jr. , Donald B. Hay , Thomas E. Cooper , Serge F. Fourcand , Long V. Vo
IPC分类号： H04L1250
CPC分类号： H04J3/1611 , H04L49/15
摘要： A bus control module for a delivery unit, which interfaces an optical fiber network to a switching matrix. The bus control module controls transport of control data and network data between various application modules of the delivery unit. The control data and network data are carried as datagrams on ingress links from the application modules and on egress links to the application modules.
摘要翻译：一种用于传送单元的总线控制模块，其将光纤网络连接到交换矩阵。总线控制模块控制传送单元的各个应用模块之间的控制数据和网络数据的传输。控制数据和网络数据作为来自应用模块的入口链路和到应用模块的出口链路的数据报携带。

6. 发明授权

US5493565A Grooming device for streamlining a plurality of input signal lines into a grouped set of output signals 失效
标题翻译：用于将多个输入信号线简化成分组的输出信号组的整理装置
公开(公告)号：US5493565A
公开(公告)日：1996-02-20
申请号：US288330
申请日：1994-08-10
申请人： Gary D. Hanson , Richard Schroder , E. Lawrence Read , Steven D. Sensel , Long V. Vo
发明人： Gary D. Hanson , Richard Schroder , E. Lawrence Read , Steven D. Sensel , Long V. Vo
IPC分类号： H04J3/00 , H04J3/04 , H04J3/08 , H04J3/16 , H04Q11/04 , H04J3/06 , H04L7/033
CPC分类号： H04Q11/0421 , H04J3/1611 , H04Q2213/1301 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13292
摘要： A grooming device (18) includes an inbound crosspoint switch (30) that combines proprietary STS-1 signals from any of a plurality of optical terminators (16) into a grouped set of output signals for transmission to a broadband matrix subsystem through dedicated matrix interfaces (20). The inbound crosspoint switch (30) includes a crosspoint matrix (72) that receives each of the plurality of input signal lines at each output signal port and selects which input signal line is connected to which output signal port as determined by a microprocessor controller (78). Each output signal port has a register (90) for storing information as to which input signal line is to be connected to that port. A decoder (92) generates a control signal from the information stored in the register (90) to drive a multiplexer (94) for selection of the appropriate input signal line.
摘要翻译：梳理装置（18）包括入站交叉点开关（30），其将来自多个光学终端器（16）中的任一个的专有STS-1信号组合成分组的输出信号组，以通过专用矩阵接口传输到宽带矩阵子系统（20）。入站交叉点开关（30）包括交叉点矩阵（72），其接收每个输出信号端口处的多个输入信号线中的每一个，并且选择哪个输入信号线连接到由微处理器控制器（78）确定的哪个输出信号端口）。每个输出信号端口具有用于存储关于哪个输入信号线将被连接到该端口的信息的寄存器（90）。解码器（92）根据存储在寄存器（90）中的信息产生控制信号，以驱动多路复用器（94）以选择合适的输入信号线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式