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1. 发明授权

US10573356B2 Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权
公开(公告)号：US10573356B2
公开(公告)日：2020-02-25
申请号：US15851197
申请日：2017-12-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sang-Uhn Cha , Young-Hun Seo , Kwang-Il Park , Seung-Jun Bae
IPC分类号： G06F11/00 , G11C7/10 , G11C11/4093 , G11C11/4096 , H03M13/00 , G06F11/10
摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

2. 发明授权

US09264039B2 Circuit and method for on-die termination, and semiconductor memory device including the same 有权
标题翻译：用于片上端接的电路和方法，以及包括其的半导体存储器件
公开(公告)号：US09264039B2
公开(公告)日：2016-02-16
申请号：US14202323
申请日：2014-03-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ho-Seok Seol , Seung-Jun Bae , Young-Soo Sohn , Ho-Sung Song
IPC分类号： H03K17/16 , H03K19/003 , H03K19/00
CPC分类号： H03K19/0005
摘要： An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.
摘要翻译：片上终端（ODT）电路包括校准单元，偏移码生成单元，加法器和ODT单元。校准单元生成一个上拉代码和一个下拉代码。偏移码基于模式寄存器设置信号，上拉代码和下拉码产生上拉偏移码和下拉偏移码。加法器分别将上拉偏移代码和下拉偏移代码加到上拉代码和下拉代码，并产生一个上拉校准代码和一个下拉校准代码。 ODT单元根据上拉校准代码和下拉校准代码改变ODT电阻。

3. 发明授权

US08576650B2 Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments 有权
公开(公告)号：US08576650B2
公开(公告)日：2013-11-05
申请号：US13790306
申请日：2013-03-08
申请人： Samsung Electronics Co., Ltd.
发明人： Tae-Young Oh , Seung-Jun Bae , Kwnag-Il Park
IPC分类号： G11C7/02
CPC分类号： G11C7/10 , G11C7/02
摘要： A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

4. 发明授权

US11216339B2 Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权
公开(公告)号：US11216339B2
公开(公告)日：2022-01-04
申请号：US17105205
申请日：2020-11-25
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Hun Seo , Kwang-Il Park , Seung-Jun Bae , Sang-Uhn Cha
IPC分类号： G06F11/00 , G06F11/10 , G11C29/52 , G11C11/4093 , H01L25/065
摘要： A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

5. 发明授权

US09461656B2 Injection-locked phase locked loop circuits using delay locked loops 有权
标题翻译：使用延迟锁定环的注入锁相环路电路
公开(公告)号：US09461656B2
公开(公告)日：2016-10-04
申请号：US14558072
申请日：2014-12-02
申请人： Samsung Electronics Co., Ltd.
发明人： Hye-Yoon Joo , Seung-Jun Bae , Young-Soo Sohn , Ho-Sung Song , Jeong-Don Ihm
IPC分类号： H03L7/06 , H03L7/087 , H03L7/07 , H03L7/083 , H03L7/099 , G11C7/22
CPC分类号： H03L7/087 , G11C7/222 , H03L7/07 , H03L7/083 , H03L7/0995
摘要： An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.
摘要翻译：注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。将DLL时钟作为VCO的注入时钟注入到VCO中。

6. 发明授权

US09424897B2 Equalizer and semiconductor memory device including the same 有权
标题翻译：均衡器和包括其的半导体存储器件
公开(公告)号：US09424897B2
公开(公告)日：2016-08-23
申请号：US14165990
申请日：2014-01-28
申请人： Samsung Electronics Co., Ltd.
发明人： Dae-Hyun Kim , Seung-Jun Bae , Kyung-Soo Ha
IPC分类号： G11C7/22 , H03K19/003 , G11C7/10 , H03K19/094
CPC分类号： G11C7/22 , G11C7/1048 , G11C7/1057 , H03K19/00361 , H03K19/09429
摘要： Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.
摘要翻译：提供了一种均衡器和包括该均衡器的半导体存储器件。均衡器包括延迟电路和反相电路。延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。均衡器被配置为使得当延迟电路输出延迟信号时，均衡器作为放大输入信号并输出放大的输入信号的感应偏置电路工作，并且当延迟电路输出反相信号时，均衡器作为锁存器电路存储和输出输入信号。

7. 发明授权

US10884852B2 Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权
公开(公告)号：US10884852B2
公开(公告)日：2021-01-05
申请号：US16228560
申请日：2018-12-20
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Hun Seo , Kwang-Il Park , Seung-Jun Bae , Sang-Uhn Cha
IPC分类号： G06F11/00 , G06F11/10 , G11C29/52 , G11C11/4093 , H01L25/065
摘要： A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

8. 发明授权

US09742355B2 Buffer circuit robust to variation of reference voltage signal 有权
公开(公告)号：US09742355B2
公开(公告)日：2017-08-22
申请号：US14959195
申请日：2015-12-04
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoon-Joo Eom , Seung-Jun Bae , Dae-Sik Moon , Joon-Young Park , Min-Su Ahn
IPC分类号： H03F3/45 , H03D7/14 , H03K19/003
CPC分类号： H03D7/1441 , H03F3/45183 , H03F2203/45051 , H03F2203/45466 , H03F2203/45674 , H03F2203/45702 , H03K19/00361
摘要： A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

9. 发明授权

US09214202B2 Input buffer and memory device including the same 有权
标题翻译：输入缓冲器和包含相同的存储器件
公开(公告)号：US09214202B2
公开(公告)日：2015-12-15
申请号：US14644339
申请日：2015-03-11
申请人： Samsung Electronics Co., Ltd.
发明人： Yong Shim , Seung-Jun Bae , Won-Joo Yun
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C7/1084 , G11C7/1054
摘要： An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.
摘要翻译：输入缓冲器包括第一缓冲器，反馈电路和第二缓冲电路。反馈电路包括反馈电阻和反馈反馈器。第一缓冲器可以被配置为基于输入信号将放大信号输出到第一缓冲器的输出节点。连接到第一缓冲器的输出节点的反馈电路可以被配置为控制放大信号。第二缓冲电路可以被配置为通过缓冲放大信号来输出缓冲器输出信号。反馈电阻器可以从第一缓冲器的输出节点接收放大信号，并向反馈节点提供反馈信号。反馈逆变器连接在反馈节点和输出节点之间。反馈反相器可以被配置为基于反馈信号来控制放大信号。

10. 发明授权

US09053774B2 Duty cycle corrector and systems including the same 有权
标题翻译：占空比校正器和系统包括相同
公开(公告)号：US09053774B2
公开(公告)日：2015-06-09
申请号：US14066193
申请日：2013-10-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ho-Seok Seol , Seung-Jun Bae , Ho-Sung Song
IPC分类号： G11C7/00 , G11C8/18 , H03K5/156 , G11C29/02
CPC分类号： G11C8/18 , G11C29/023 , G11C29/028 , H03K5/1565
摘要： A duty cycle corrector includes a sensing unit, a pad unit, a fuse unit, and a driver unit. The sensing unit generates at least one sensing signal based on the sensed duty cycle ratio of an output signal. The pad unit outputs at least one decision signal based on the at least one sensing signal. The fuse unit generates a duty cycle control signal based on at least one received fuse control signal. The driver unit adjusts a duty cycle ratio of an input signal to generate the output signal based on the duty cycle control signal. The driver unit adjusts the duty cycle ratio of the input signal by adjusting a pull-up strength or a pull-down strength of the input signal based on the duty cycle control signal.
摘要翻译：占空比校正器包括感测单元，衬垫单元，保险丝单元和驱动单元。感测单元基于感测到的输出信号的占空比来产生至少一个感测信号。垫单元基于至少一个感测信号输出至少一个判定信号。熔丝单元基于至少一个接收的熔丝控制信号产生占空比控制信号。驱动单元根据占空比控制信号来调整输入信号的占空比，生成输出信号。驱动器单元通过基于占空比控制信号调整输入信号的上拉强度或下拉强度来调节输入信号的占空比。

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