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1. 再颁专利

USRE46348E1 Program cycle skip 有权
公开(公告)号：USRE46348E1
公开(公告)日：2017-03-21
申请号：US14231591
申请日：2014-03-31
申请人： SANDISK 3D, LLC
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00 , G11C13/00 , G11C5/02 , G11C17/16 , G11C17/18
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

2. 发明申请

US20160232969A1 Independent Sense Amplifier Addressing And Quota Sharing In Non-Volatile Memory 有权
标题翻译：独立检测放大器在非易失性存储器中的寻址和配额共享
公开(公告)号：US20160232969A1
公开(公告)日：2016-08-11
申请号：US14619985
申请日：2015-02-11
申请人： SANDISK 3D LLC
发明人： Gopinath Balakrishnan , Yibo Yin , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C8/12 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0097 , G11C2013/0076 , G11C2013/0088
摘要： Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.
摘要翻译：独立读出放大器寻址在一个列地址周期内为单个托架内的各个读出放大器组提供单独的列地址。存储器系统确定是否可以跳过单个存储单元或一个隔行列中的位。对于具有需要编程的至少一个存储单元（或位）的每个读出放大器组，系统确定第一列地址是否可以跳过存储器单元。如果可以跳过来自读出放大器组的第一列地址的位或存储单元，则系统从需要编程的组确定具有列地址的下一位。系统在第一列地址周期中对下一列地址进行分组编程。在单列地址周期期间，系统可以为托架内的不同读出放大器组编程不同的列地址。

3. 发明授权

US09318194B1 Apparatus and methods for sensing hard bit and soft bits 有权
标题翻译：用于感测硬位和软位的装置和方法
公开(公告)号：US09318194B1
公开(公告)日：2016-04-19
申请号：US14500476
申请日：2014-09-29
申请人： SanDisk 3D LLC
发明人： Chang Siau , Jeffrey Koon Yee Lee , Tianhong Yan , Yingchang Chen , Gopinath Balakrishnan , Tz-yi Liu
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.
摘要翻译：提供一种用于读取非易失性存储器系统的存储单元的方法。该方法包括在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内为存储器单元生成硬比特和N个软比特。

4. 发明申请

US20160042771A1 TIMED MULTIPLEX SENSING 有权
公开(公告)号：US20160042771A1
公开(公告)日：2016-02-11
申请号：US14887547
申请日：2015-10-20
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C7/08 , G11C16/26 , G11C16/04 , G11C13/00
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

5. 发明授权

US09245599B1 Timed multiplex sensing 有权
公开(公告)号：US09245599B1
公开(公告)日：2016-01-26
申请号：US14887547
申请日：2015-10-20
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C13/00 , G11C7/08 , G11C16/26 , G11C16/04
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

6. 发明授权

US09711225B2 Regrouping and skipping cycles in non-volatile memory 有权
公开(公告)号：US09711225B2
公开(公告)日：2017-07-18
申请号：US14515387
申请日：2014-10-15
申请人： SanDisk 3D LLC
发明人： Gopinath Balakrishnan
IPC分类号： G11C7/00 , G11C16/10 , G06F12/02 , G11C7/10 , G11C13/00
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7208 , G11C7/1006 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped into new bay groups to reduce the number of BAD cycles during programming. Independent column addressing for multiple bays within a bay group is provided. During a column address cycle, a separate column address is provided to the bays to select different columns for programming within each bay. By simultaneously programming multiple column addresses during a single column address cycle, the system may skip programming for some column address cycles.

7. 发明授权

US09564215B2 Independent sense amplifier addressing and quota sharing in non-volatile memory 有权
标题翻译：独立读出放大器在非易失性存储器中寻址和配额共享
公开(公告)号：US09564215B2
公开(公告)日：2017-02-07
申请号：US14619985
申请日：2015-02-11
申请人： SanDisk 3D LLC
发明人： Gopinath Balakrishnan , Yibo Yin , Tianhong Yan
IPC分类号： G11C8/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C8/12 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0097 , G11C2013/0076 , G11C2013/0088
摘要： Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.
摘要翻译：独立读出放大器寻址在一个列地址周期内为单个托架内的各个读出放大器组提供单独的列地址。存储器系统确定是否可以跳过单个存储单元或一个隔行列中的位。对于具有需要编程的至少一个存储单元（或位）的每个读出放大器组，系统确定第一列地址是否可以跳过存储器单元。如果可以跳过来自读出放大器组的第一列地址的位或存储单元，则系统从需要编程的组确定具有列地址的下一位。系统在第一列地址周期中对下一列地址进行分组编程。在单列地址周期期间，系统可以为托架内的不同读出放大器组编程不同的列地址。

8. 发明申请

US20160093373A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 有权
公开(公告)号：US20160093373A1
公开(公告)日：2016-03-31
申请号：US14500476
申请日：2014-09-29
申请人： SanDisk 3D LLC
发明人： Chang Siau , Jeffrey Koon Yee Lee , Tianhong Yan , Yingchang Chen , Gopinath Balakrishnan , Tz-yi Liu
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

9. 发明申请

US20140281135A1 Dynamic Address Grouping For Parallel Programming In Non-Volatile Memory 有权
标题翻译：用于非易失性存储器中并行编程的动态地址分组
公开(公告)号：US20140281135A1
公开(公告)日：2014-09-18
申请号：US13839300
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Gopinath Balakrishnan , Tz-Yi Liu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C7/1006 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses.
摘要翻译：非易失性存储器系统在写入之前评估用户数据，以便在一个周期内潜在的组地址进行写入。该系统可以确定在列地址周期中将编程列地址的哪个读出放大器地址。将编程的位数与允许的并行位数进行比较。该系统基于比较产生一组读出放大器地址。系统生成组，其中包括要编程的总位数在允许的并行位数内。每组在一个读出放大器地址周期中进行编程。多个读出放大器地址可以分组编程，同时仍然保留在允许的并行编程位数中。该系统在写入操作之前进行读取，并产生对应读出放大器地址的分组信息的位图数据。

10. 再颁专利

USRE46154E1 Page buffer program command and methods to reprogram pages without re-inputting data to a memory device 有权
公开(公告)号：USRE46154E1
公开(公告)日：2016-09-20
申请号：US14285829
申请日：2014-05-23
申请人： SanDisk 3D LLC
发明人： Luca Fasoli , Yuheng Zhang , Gopinath Balakrishnan
IPC分类号： G06F12/00 , G11C16/10
CPC分类号： G11C16/102 , G06F12/0246
摘要： A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.

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