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1. 发明申请

US20160315095A1 BLOCKING OXIDE IN MEMORY OPENING INTEGRATION SCHEME FOR THREE-DIMENSIONAL MEMORY STRUCTURE 有权
标题翻译：存储器中的阻塞氧化物开放三维存储器结构的集成方案
公开(公告)号：US20160315095A1
公开(公告)日：2016-10-27
申请号：US14921385
申请日：2015-10-23
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jongsun Sel , Chan Park , Atsushi Suyama , Frank Yu , Hiroyuki Ogawa , Ryoichi Honma , Kensuke Yamaguchi , Hiroaki Iuchi , Naoki Takeguchi , Tuan Pham , Kiyohiko Sakakibara , Jiao Chen
IPC分类号： H01L27/115 , H01L29/16 , H01L21/311 , H01L29/788 , H01L21/28 , H01L29/04 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/04 , H01L29/16 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
摘要翻译：绝缘层和牺牲材料层的交替堆叠形成在衬底上。在形成存储器开口之后，通过形成至少一个氧化硅部分，将存储器开口的所有表面设置为氧化硅表面。在存储器开口中形成氮化硅层。在形成存储器堆叠结构之后，可以使用氧化硅部分作为蚀刻停止来形成背面凹部。随后可以使用氮化硅层作为蚀刻停止物去除氧化硅部分。氮化硅层的物理暴露部分可以被选择性地移除到存储器堆叠结构。可以通过连续使用蚀刻停止结构来最小化或消除对存储器堆叠结构的外层的损坏。随后可以在背面凹槽中形成导电层。

2. 发明申请

US20160343718A1 Memory Hole Last Boxim 有权
标题翻译：记忆孔最后一次
公开(公告)号：US20160343718A1
公开(公告)日：2016-11-24
申请号：US14928385
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Zhenyu Lu , Hiro Kinoshita , Daxin Mao , Johann Alsmeier , Wenguang Shi , Yingda Dong , Henry Chien , Kensuke Yamaguchi , Xiaolong Hu
IPC分类号： H01L27/115 , H01L23/532 , H01L21/768
CPC分类号： H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.
摘要翻译：公开了用于形成3D存储器阵列的技术。存储器开口填充有牺牲材料，例如硅或氮化物。之后，使用替代技术从ONON堆叠中去除氮化物，并用诸如钨的导电材料代替它。之后，存储单元薄膜形成在存储器开口中。导电材料用作存储器单元的控制栅极。控制门不会受到角落四舍五入的影响。 ONON收缩被避免，这将阻止控制门收缩。在控制栅极更换之后，电荷存储区域和控制栅极之间的块状氧化物可能被沉积，因此均匀性良好。在控制栅极更换之后，可以沉积块状氧化物，因此与控制栅极相邻的TiN可以更厚，以防止氟侵蚀相邻控制栅极之间的绝缘体。因此，防止控制门短路的控制门。

3. 发明授权

US09716101B2 Forming 3D memory cells after word line replacement 有权
公开(公告)号：US09716101B2
公开(公告)日：2017-07-25
申请号：US14928385
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Zhenyu Lu , Hiro Kinoshita , Daxin Mao , Johann Alsmeier , Wenguang Shi , Yingda Dong , Henry Chien , Kensuke Yamaguchi , Xiaolong Hu
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L27/11575
CPC分类号： H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

4. 发明授权

US09601508B2 Blocking oxide in memory opening integration scheme for three-dimensional memory structure 有权
公开(公告)号：US09601508B2
公开(公告)日：2017-03-21
申请号：US14921385
申请日：2015-10-23
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jongsun Sel , Chan Park , Atsushi Suyama , Frank Yu , Hiroyuki Ogawa , Ryoichi Honma , Kensuke Yamaguchi , Hiroaki Iuchi , Naoki Takeguchi , Tuan Pham , Kiyohiko Sakakibara , Jiao Chen
IPC分类号： H01L27/115 , H01L29/04 , H01L29/16 , H01L21/02 , H01L29/788 , H01L21/28 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/04 , H01L29/16 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

5. 发明授权

US09553100B2 Selective floating gate semiconductor material deposition in a three-dimensional memory structure 有权
标题翻译：选择性浮栅半导体材料沉积在三维存储器结构中
公开(公告)号：US09553100B2
公开(公告)日：2017-01-24
申请号：US14560351
申请日：2014-12-04
申请人： SanDisk Technologies, Inc.
发明人： Hiroyuki Kamiya , Kensuke Yamaguchi
IPC分类号： H01L27/11 , H01L27/115 , H01L21/02 , H01L21/28 , H01L21/3065 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11556 , H01L21/0206 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02247 , H01L21/02252 , H01L21/02255 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02636 , H01L21/02639 , H01L21/28273 , H01L21/28282 , H01L21/3065 , H01L21/3105 , H01L21/32135 , H01L27/11519 , H01L27/11521 , H01L27/11582 , H01L29/42324 , H01L29/7883 , H01L29/7889
摘要： A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.
摘要翻译：形成三维存储器件的方法包括在衬底上形成交替的第一和第二材料层的堆叠，形成通过堆叠的存储器开口，在存储器开口中形成存储膜和半导体沟道，以及形成背面凹槽通过去除对第一材料层和存储膜有选择性的第二材料层，其中记忆膜的外侧壁在每个后侧凹槽内物理地暴露。该方法还包括在后侧凹槽中的存储膜上形成选自第一材料层上的硅沉积抑制表面和硅沉积促进表面的至少一组表面，在每个背面凹槽内侧向选择性地生长含硅半导体部分在所述背面凹槽内形成至少一个阻挡电介质，以及通过在所述背面凹槽内沉积导电材料来形成导电材料层。

6. 发明申请

US20160111439A1 BOTTOM RECESS PROCESS FOR AN OUTER BLOCKING DIELECTRIC LAYER INSIDE A MEMORY OPENING 有权
标题翻译：内部开放内部阻塞介质层的底部回收工艺
公开(公告)号：US20160111439A1
公开(公告)日：2016-04-21
申请号：US14519733
申请日：2014-10-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： Masanori Tsutsumi , Hiroshi Sasaki , Hiroyuki Ogawa , Michiaki Sano , Masato Miyamoto , Kensuke Yamaguchi , Seiji Shimabukuro
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11529 , H01L27/11556 , H01L27/11573
摘要： A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
摘要翻译：提供了一种使存储器开口下面的半导体表面的过蚀刻或损坏最小化的方法。第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。牺牲衬垫形成在第一阻挡电介质层上。通过牺牲衬垫的水平部分形成开口。存储器开口底部的第一阻挡介电层的水平部分可以通过牺牲衬垫中的开口进行蚀刻。衬底的半导体表面可以以最小的过蚀刻和/或表面损伤物理地暴露在存储器开口的底部。可以在形成牺牲衬垫之前或之后形成第二阻挡电介质层，以提供多层阻挡电介质。

7. 发明授权

US09768270B2 Method of selectively depositing floating gate material in a memory device 有权
公开(公告)号：US09768270B2
公开(公告)日：2017-09-19
申请号：US14840474
申请日：2015-08-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： Marika Gunji-Yoneoka , Atsushi Suyama , Kensuke Yamaguchi , Hiroyuki Kinoshita , Raghuveer S. Makala , Rahul Sharangpani , Shigehisa Inoue , Tuan Pham
IPC分类号： G11C11/34 , H01L29/51 , H01L21/28 , H01L21/3213 , H01L21/311 , H01L27/11556 , H01L29/06 , H01L21/3205 , H01L21/02 , H01L27/11582
CPC分类号： H01L29/517 , H01L21/02087 , H01L21/0209 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L21/32051 , H01L21/32134 , H01L27/11556 , H01L27/11582 , H01L29/0649 , H01L29/7827
摘要： Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.

8. 发明授权

US09305937B1 Bottom recess process for an outer blocking dielectric layer inside a memory opening 有权
标题翻译：存储器开口内的外部阻塞介电层的底部凹陷工艺
公开(公告)号：US09305937B1
公开(公告)日：2016-04-05
申请号：US14519733
申请日：2014-10-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： Masanori Tsutsumi , Hiroshi Sasaki , Hiroyuki Ogawa , Michiaki Sano , Masato Miyamoto , Kensuke Yamaguchi , Seiji Shimabukuro
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11529 , H01L27/11556 , H01L27/11573
摘要： A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
摘要翻译：提供了一种使存储器开口下面的半导体表面的过蚀刻或损坏最小化的方法。第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。牺牲衬垫形成在第一阻挡电介质层上。通过牺牲衬垫的水平部分形成开口。存储器开口底部的第一阻挡介电层的水平部分可以通过牺牲衬垫中的开口进行蚀刻。衬底的半导体表面可以以最小的过蚀刻和/或表面损伤物理地暴露在存储器开口的底部。可以在形成牺牲衬垫之前或之后形成第二阻挡电介质层，以提供多层阻挡电介质。

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