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1. 发明授权

US09842851B2 Three-dimensional memory devices having a shaped epitaxial channel portion 有权
公开(公告)号：US09842851B2
公开(公告)日：2017-12-12
申请号：US14927990
申请日：2015-10-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jayavel Pachamuthu , Tuan Pham
IPC分类号： H01L27/11 , H01L29/78 , H01L27/11582 , H01L27/1157 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/30608 , H01L21/3065 , H01L27/1157
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.

2. 发明申请

US20160315095A1 BLOCKING OXIDE IN MEMORY OPENING INTEGRATION SCHEME FOR THREE-DIMENSIONAL MEMORY STRUCTURE 有权
标题翻译：存储器中的阻塞氧化物开放三维存储器结构的集成方案
公开(公告)号：US20160315095A1
公开(公告)日：2016-10-27
申请号：US14921385
申请日：2015-10-23
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jongsun Sel , Chan Park , Atsushi Suyama , Frank Yu , Hiroyuki Ogawa , Ryoichi Honma , Kensuke Yamaguchi , Hiroaki Iuchi , Naoki Takeguchi , Tuan Pham , Kiyohiko Sakakibara , Jiao Chen
IPC分类号： H01L27/115 , H01L29/16 , H01L21/311 , H01L29/788 , H01L21/28 , H01L29/04 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/04 , H01L29/16 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
摘要翻译：绝缘层和牺牲材料层的交替堆叠形成在衬底上。在形成存储器开口之后，通过形成至少一个氧化硅部分，将存储器开口的所有表面设置为氧化硅表面。在存储器开口中形成氮化硅层。在形成存储器堆叠结构之后，可以使用氧化硅部分作为蚀刻停止来形成背面凹部。随后可以使用氮化硅层作为蚀刻停止物去除氧化硅部分。氮化硅层的物理暴露部分可以被选择性地移除到存储器堆叠结构。可以通过连续使用蚀刻停止结构来最小化或消除对存储器堆叠结构的外层的损坏。随后可以在背面凹槽中形成导电层。

3. 发明授权

US09460958B2 Air gap isolation in non-volatile memory 有权
公开(公告)号：US09460958B2
公开(公告)日：2016-10-04
申请号：US14091101
申请日：2013-11-26
申请人： SanDisk Technologies Inc.
发明人： Vinod R Purayath , Hiroyuki Kinoshita , Tuan Pham
IPC分类号： H01L21/76 , H01L21/764 , H01L27/115
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

4. 发明授权

US08879331B2 Shared bit line string architecture 有权
标题翻译：共享位线字符串架构
公开(公告)号：US08879331B2
公开(公告)日：2014-11-04
申请号：US13797298
申请日：2013-03-12
申请人： Sandisk Technologies Inc.
发明人： Jongsun Sel , Seungpil Lee , Kwang-Ho Kim , Tuan Pham
IPC分类号： G11C11/34 , G11C16/24
CPC分类号： G11C16/24 , G11C7/12 , G11C7/18 , G11C16/0483 , G11C2207/002
摘要： Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
摘要翻译：描述使用共享位线串结构对存储器单元进行编程和读取的方法。在一些实施例中，存储器单元和选择器件可以对应于包括电荷存储层的晶体管。在一些情况下，电荷存储层可以是导电的（例如，在浮栅器件中使用的多晶硅层）或非导电的（例如，在SONOS器件中使用的氮化硅层）。在一些实施例中，一对串的第一串中的存储器单元的选择可以包括将SEO晶体管设置为导通状态，并将控制漏极侧选择晶体管的SGD线设置为大于第一阈值电压与第一串的第一漏极侧选择晶体管相关联，并且小于与该对串的第二串的第二漏极侧选择晶体管相关联的第二阈值电压。

5. 发明申请

US20140120692A1 Air Gap Isolation In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的空气间隙隔离
公开(公告)号：US20140120692A1
公开(公告)日：2014-05-01
申请号：US14091101
申请日：2013-11-26
申请人： SanDisk Technologies Inc.
发明人： Vinod R. Purayath , Hiroyuki Kinoshita , Tuan Pham
IPC分类号： H01L21/764 , H01L27/115
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地可以通过在活动区域之间沿列方向延伸的位线空气间隙来提供衬底的相邻有源区域之间的电隔离。在每个隔离区域上形成至少一个盖，至少部分覆盖空气以提供相应气隙的上端点。帽可以至少部分地沿着相邻的电荷存储区域的侧壁形成。在各种实施方案中，选择性生长方法用于在隔离区域上形成封盖条以限定气隙。还提供了在相邻行存储元件之间沿行方向延伸的字线气隙。

6. 发明申请

US20130334587A1 Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory 有权
标题翻译：金属控制门结构和非易失性存储器中的空气间隙隔离
公开(公告)号：US20130334587A1
公开(公告)日：2013-12-19
申请号：US13947530
申请日：2013-07-22
申请人： SanDisk Technologies Inc.
发明人： Vinod Robert Purayath , Tuan Pham , Hiroyuki Kinoshita , Yuan Zhang , Henry Chin , James K. Kai , Takashi W. Orimoto , George Matamis , Henry Chien
IPC分类号： H01L27/115
CPC分类号： H01L27/11517 , H01L21/28273 , H01L21/764 , H01L21/7682 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
摘要翻译：提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

7. 发明授权

US09768270B2 Method of selectively depositing floating gate material in a memory device 有权
公开(公告)号：US09768270B2
公开(公告)日：2017-09-19
申请号：US14840474
申请日：2015-08-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： Marika Gunji-Yoneoka , Atsushi Suyama , Kensuke Yamaguchi , Hiroyuki Kinoshita , Raghuveer S. Makala , Rahul Sharangpani , Shigehisa Inoue , Tuan Pham
IPC分类号： G11C11/34 , H01L29/51 , H01L21/28 , H01L21/3213 , H01L21/311 , H01L27/11556 , H01L29/06 , H01L21/3205 , H01L21/02 , H01L27/11582
CPC分类号： H01L29/517 , H01L21/02087 , H01L21/0209 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L21/32051 , H01L21/32134 , H01L27/11556 , H01L27/11582 , H01L29/0649 , H01L29/7827
摘要： Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.

8. 发明授权

US09099532B2 Processes for NAND flash memory fabrication 有权
标题翻译： NAND闪存制造工艺
公开(公告)号：US09099532B2
公开(公告)日：2015-08-04
申请号：US13775023
申请日：2013-02-22
申请人： SanDisk Technologies Inc.
发明人： Jongsun Sel , Tuan Pham
IPC分类号： H01L21/768 , H01L21/033 , H01L27/115 , H01L21/28 , H01L21/3213
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/28273 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11529
摘要： Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.
摘要翻译：使用双重图案化工艺在NAND闪存阵列中形成窄字线，其中侧壁间隔物限定字线。侧壁间隔物还限定选择栅极的边缘，使得选择栅极和最近的字线之间的间距等于相邻字线之间的间隔。

9. 发明申请

US20140312403A1 Memory Cell Floating Gate Replacement 有权
标题翻译：内存单元浮动门更换
公开(公告)号：US20140312403A1
公开(公告)日：2014-10-23
申请号：US13865865
申请日：2013-04-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jongsun Sel , Tuan Pham , Ming Tian
IPC分类号： H01L29/788 , H01L29/66
CPC分类号： H01L29/788 , G11C16/0408 , H01L21/28273 , H01L27/11524 , H01L27/11529 , H01L27/11541 , H01L27/11543 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.
摘要翻译：通过沉积两个N型多晶硅层形成NAND闪存芯片。上部N型多晶硅层仅在阵列区域中被P型多晶硅和阻挡层代替，同时保持上部N型多晶硅层在外围。以这种方式，浮置栅极基本为P型，而外围晶体管的栅极为N型。

10. 发明申请

US20140269100A1 SHARED BIT LINE STRING ARCHITECTURE 有权
标题翻译：共享点行线建筑
公开(公告)号：US20140269100A1
公开(公告)日：2014-09-18
申请号：US13797298
申请日：2013-03-12
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jongsun Sel , Seungpil Lee , Kwang-Ho Kim , Tuan Pham
IPC分类号： G11C16/24
CPC分类号： G11C16/24 , G11C7/12 , G11C7/18 , G11C16/0483 , G11C2207/002
摘要： Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
摘要翻译：描述使用共享位线串结构对存储器单元进行编程和读取的方法。在一些实施例中，存储器单元和选择器件可以对应于包括电荷存储层的晶体管。在一些情况下，电荷存储层可以是导电的（例如，在浮栅器件中使用的多晶硅层）或非导电的（例如，在SONOS器件中使用的氮化硅层）。在一些实施例中，一对串的第一串中的存储器单元的选择可以包括将SEO晶体管设置为导通状态，并将控制漏极侧选择晶体管的SGD线设置为大于第一阈值电压与第一串的第一漏极侧选择晶体管相关联，并且小于与该对串的第二串的第二漏极侧选择晶体管相关联的第二阈值电压。

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