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1. 发明授权

US11289486B2 Semiconductor memory device, method of driving the same and method of fabricating the same 有权
公开(公告)号：US11289486B2
公开(公告)日：2022-03-29
申请号：US16366967
申请日：2019-03-27
申请人： SK hynix Inc. , Jin Hong Ahn , Duality Inc.
发明人： Jin Hong Ahn
IPC分类号： G11C11/40 , H01L27/108 , G11C11/4093 , H01L29/10 , H01L29/78 , G11C11/4096 , G11C11/406 , H01L21/02 , H01L21/28 , G11C11/404 , H01L29/08 , H01L29/423
摘要： A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

2. 发明授权

US11508728B2 Semiconductor memory device, method of driving the same and method of fabricating the same 有权
公开(公告)号：US11508728B2
公开(公告)日：2022-11-22
申请号：US17401615
申请日：2021-08-13
申请人： SK hynix Inc. , Jin Hong Ahn , Duality Inc.
发明人： Jin Hong Ahn
IPC分类号： H01L27/108 , G11C11/4093 , H01L29/10 , H01L29/78 , G11C11/4096 , G11C11/406 , H01L21/02 , H01L21/28 , G11C11/404 , H01L29/08 , H01L29/423
摘要： A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

3. 发明授权

US11456297B2 Semiconductor memory device, method of driving the same and method of fabricating the same 有权
公开(公告)号：US11456297B2
公开(公告)日：2022-09-27
申请号：US17401601
申请日：2021-08-13
申请人： SK hynix Inc. , Jin Hong Ahn , Duality Inc.
发明人： Jin Hong Ahn
IPC分类号： G11C11/40 , H01L27/108 , G11C11/4093 , H01L29/10 , H01L29/78 , G11C11/4096 , G11C11/406 , H01L21/02 , H01L21/28 , G11C11/404 , H01L29/08 , H01L29/423
摘要： A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

4. 发明申请

US20080151649A1 NONVOLATILE LATCH CIRCUIT AND SYSTEM ON CHIP WITH THE SAME 有权
标题翻译：非线性锁芯电路及其芯片系统
公开(公告)号：US20080151649A1
公开(公告)日：2008-06-26
申请号：US12046351
申请日：2008-03-11
申请人： Hee Bok KANG , Jin Hong Ahn
发明人： Hee Bok KANG , Jin Hong Ahn
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/22
摘要： A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time. The nonvolatile latch circuit does not require an additional data storage period but detects change of latch data in the active period to store new data in a nonvolatile latch unit. When power is accidentally off, new data are constantly stored in the nonvolatile latch unit, thereby preventing data loss and improving an operating speed without a booting time for restoring data.
摘要翻译：一种非易失性锁存电路和芯片上的系统，具有相同的特征检测在活动期间锁存数据的变化，以将新数据存储在锁存器中，而不需要额外的数据存储时间。非易失性锁存电路不需要额外的数据存储周期，而是在活动期间检测锁存数据的变化，以将新数据存储在非易失性锁存单元中。当电源意外关闭时，新数据不断存储在非易失性锁存单元中，从而防止数据丢失，提高运行速度，而无需启动恢复数据的时间。

5. 发明授权

US07352605B2 Nonvolatile ferroelectric memory device and method thereof 有权
标题翻译：非易失性铁电存储器件及其方法
公开(公告)号：US07352605B2
公开(公告)日：2008-04-01
申请号：US11482128
申请日：2006-07-07
申请人： Hee Bok Kang , Jin Hong Ahn
发明人： Hee Bok Kang , Jin Hong Ahn
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , H01L27/11502 , H01L28/55
摘要： A nonvolatile ferroelectric memory device has a plurality of ferroelectric memory cells. The ferroelectric memory cells include a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the floating channel layer corresponding to the bit of datum stored in the first double gate cell; and a second double gate cell selectively turned on by a potential on a selection line to supply a potential of a sense line to the first double gate cell to control read and write operations of the first double gate cell. The present invention also provides methods for operating the nonvolatile ferroelectric memory device.
摘要翻译：非易失性铁电存储器件具有多个铁电存储单元。铁电存储单元包括用于存储一比特数据的第一双栅极单元，第一双栅极单元包括铁电层和浮动沟道层，其中，强电介质层的极性状态影响浮动沟道层的电阻，对应于存储在第一双门单元中的基准的位的浮动通道层的电阻; 并且通过选择线上的电位选择性地导通第二双栅电池，以将感测线的电位提供给第一双栅极单元，以控制第一双栅极单元的读和写操作。本发明还提供了用于操作非易失性铁电存储器件的方法。

6. 发明授权

US07269054B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07269054B2
公开(公告)日：2007-09-11
申请号：US11296431
申请日：2005-12-08
申请人： Hee Bok Kang , Jin Hong Ahn
发明人： Hee Bok Kang , Jin Hong Ahn
IPC分类号： G11C11/00 , G11C11/34
CPC分类号： G11C11/413 , G11C7/20 , G11C14/00 , G11C14/0063 , H01L29/7881
摘要： A nonvolatile semiconductor memory device is provided for a high-powered system without the need for an additional system setting process to set the system initialization state after power-on to the previous state. The nonvolatile semiconductor memory device comprises a pull-up driving unit configured to include a plurality of nonvolatile cells for storing inputted data and to pull up a storage node, a pull-down driving unit configured to pull down the storage node, and a plurality of data registers including a data input/output unit configured to selectively input/output data between a bit line and the storage node depending on a voltage applied to a word line.
摘要翻译：为大功率系统提供非易失性半导体存储器件，而不需要额外的系统设置过程，以在上电之后将系统初始化状态设置为先前状态。非易失性半导体存储器件包括：上拉驱动单元，被配置为包括多个非易失性单元，用于存储输入的数据并上拉存储节点;下拉驱动单元，被配置为下拉存储节点;以及多个数据寄存器，包括数据输入/输出单元，其配置为根据施加到字线的电压来选择性地在位线和存储节点之间输入/输出数据。

7. 发明授权

US07151034B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US07151034B2
公开(公告)日：2006-12-19
申请号：US11165178
申请日：2005-06-24
申请人： Sang Don Lee , Yil Wook Kim , Jin Hong Ahn
发明人： Sang Don Lee , Yil Wook Kim , Jin Hong Ahn
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78609 , H01L29/78621
摘要： The present invention discloses improved semiconductor device and method for manufacturing wherein one side of a source and drain region and a portion of a channel region are disposed on a buried oxide layer formed on a semiconductor substrate and the side of the source and drain region and another portion of the channel region are disposed on a Si epitaxial layer formed on a semiconductor substrate.

8. 发明授权

US07126185B2 Charge trap insulator memory device 失效
公开(公告)号：US07126185B2
公开(公告)日：2006-10-24
申请号：US11115135
申请日：2005-04-27
申请人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
发明人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0483 , G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/7881 , H01L29/792 , H01L29/8616
摘要： A charge trap insulator memory device comprises a plurality of memory cells connected serially, a first switching device, and a second switching device. In the plurality of memory cells, data applied through a bit line depending on potentials applied to a top word line and a bottom word line are stored in a charge trap insulator or the data stored in the charge trap insulator are outputted to the bit line. The first switching element selectively connects the plurality of memory cells to the bit line in response to a first selecting signal. The second switching element selectively connects the plurality of memory cells to a sensing line in response to a second selecting signal.

9. 发明授权

US07710240B2 RFID device having nonvolatile ferroelectric capacitor 失效
标题翻译：具有非易失性铁电电容器的RFID装置
公开(公告)号：US07710240B2
公开(公告)日：2010-05-04
申请号：US11320987
申请日：2005-12-30
申请人： Hee Bok Kang , Jin Hong Ahn
发明人： Hee Bok Kang , Jin Hong Ahn
IPC分类号： H04Q5/22 , G08B13/14
CPC分类号： G06K19/07749
摘要： A capacitor applied to a voltage multiplier and a modulator/demodulator of a RFID device is formed as a nonvolatile ferroelectric capacitor formed by the same process of a memory cell capacitor. The nonvolatile ferroelectric capacitor has a high dielectric constant to reduce the area of the capacitor.
摘要翻译：形成用于RFID装置的电压倍增器和调制器/解调器的电容器，作为通过存储单元电容器的相同处理而形成的非易失性铁电电容器。非易失性铁电电容器具有高的介电常数以减小电容器的面积。

10. 发明授权

US07310268B2 Float gate memory device 失效
标题翻译：浮动门存储器件
公开(公告)号：US07310268B2
公开(公告)日：2007-12-18
申请号：US11115301
申请日：2005-04-27
申请人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
发明人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0408 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/7881
摘要： A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on the float channel, data are stored. Here, data are written in the float gate depending on levels of the bottom word line and the top word line, and different channel resistances are induced to the float channel depending on polarity states of charges stored in the float gate, so that data are read. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.
摘要翻译：浮动栅极存储器件包括底部字线，形成在底部字线上并保持在浮置状态的浮动沟道层，浮动栅极和形成在浮动栅极上的与底部字线平行的顶部字线。在浮动通道上形成的浮动门中，存储数据。这里，根据底部字线和顶部字线的电平，将数据写入浮动栅极，并且根据存储在浮动栅极中的电荷的极性状态，将不同的通道电阻感应到浮动通道，从而读取数据。结果，在浮栅存储器件中，由于使用多个单元氧化物层垂直淀积的多个浮栅单元阵列，保持特性得到改善，并且单元集成能力也增加。

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