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1. 发明申请

US20150170746A1 Optimizing Pass Voltage And Initial Program Voltage Based On Performance Of Non-Volatile Memory 有权
标题翻译：基于非易失性存储器的性能优化通过电压和初始编程电压
公开(公告)号：US20150170746A1
公开(公告)日：2015-06-18
申请号：US14108677
申请日：2013-12-17
申请人： SanDisk Technologies Inc.
发明人： Ken Oowada , Shota Murai
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： A programming techniques adaptively sets a pass voltage and an initial program voltage based on a programming speed of a set of memory cells. In one pass of a multi-pass programming operation, a programming speed-indicating program voltage is obtained. For example, this can be a final program voltage or a program voltage at another programming milestone. A pass voltage is determined for another programming pass of the multi-pass programming operation, by providing an adjustment to a reference pass voltage. An initial program voltage is determined for the another programming pass based on an offset from the programming speed-indicating program voltage. The initial program voltage is further adjusted to counteract an effect of the adjustment to a reference pass voltage. The adjustment to the initial program voltage is opposite in polarity and smaller in magnitude than the adjustment to the reference pass voltage.
摘要翻译：编程技术基于一组存储器单元的编程速度自适应地设置通过电压和初始编程电压。在多遍编程操作的一次通过中，获得编程速度指示程序电压。例如，这可以是另一编程里程碑的最终程序电压或编程电压。通过提供对参考通过电压的调整，确定多通道编程操作的另一编程遍的通过电压。基于与编程速度指示程序电压的偏移，为另一个编程通过确定初始编程电压。进一步调整初始编程电压以抵消对参考通过电压的调整的影响。对初始编程电压的调整在极性方面是相反的，并且在幅度上比对参考通过电压的调整要小。

2. 发明授权

US08908441B1 Double verify method in multi-pass programming to suppress read noise 有权
标题翻译：多重编程中的双重验证方法可抑制读取噪声
公开(公告)号：US08908441B1
公开(公告)日：2014-12-09
申请号：US14053866
申请日：2013-10-15
申请人： SanDisk Technologies Inc.
发明人： Deepanshu Dutta , Ken Oowada , Genki Sano , Masaaki Higashitani
IPC分类号： G11C16/34 , G11C16/10 , G11C16/12 , G11C7/08 , G11C16/04
CPC分类号： G11C16/3459 , G11C7/08 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/12
摘要： Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is indicated by a decrease in the threshold voltage of a cell when the cell is repeatedly read. In one approach, during the programming pass, a cell enters a temporary lockout state when it passes a first verify test and is subject to one or more additional verify tests. Data is stored to identify the cell as a noisy cell or a non-noisy cell based on the one or more additional verify tests. Or, the cells are subject to the one or more additional verify tests at the end of the programming pass. In a subsequent programming pass, the noisy cell is programmed using a stricter verify condition. Or, the noisy cell is kept in an erased state.
摘要翻译：在编程过程中识别具有读取噪声的存储器单元，并且与非噪声单元相比，噪声存储器单元的编程量增加。当重复读取单元时，读取噪声由单元的阈值电压的降低来表示。在一种方法中，在编程过程中，当单元通过第一验证测试并且经受一个或多个附加验证测试时，单元进入临时锁定状态。基于一个或多个附加验证测试，存储数据以将该单元识别为噪声小区或非噪声小区。或者，在编程过程结束时，对单元进行一次或多次额外的验证测试。在随后的编程过程中，使用更严格的验证条件对噪声单元进行编程。或者，嘈杂的电池被保持在擦除状态。

3. 发明申请

US20140269083A1 BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS 有权
公开(公告)号：US20140269083A1
公开(公告)日：2014-09-18
申请号：US14290891
申请日：2014-05-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

4. 发明授权

US09548130B2 Non-volatile memory with prior state sensing 有权
标题翻译：具有先前状态感测的非易失性存储器
公开(公告)号：US09548130B2
公开(公告)日：2017-01-17
申请号：US14817741
申请日：2015-08-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Dana Lee , Ken Oowada , Shih-Chung Lee
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , G11C16/10 , G11C16/28
CPC分类号： G11C16/3459 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11582
摘要： A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.
摘要翻译：非易失性存储器系统包括以三维结构排列的多个存储器单元和与存储器单元通信的一个或多个控制电路。一个或多个控制电路被配置为对存储器单元编程和验证编程。多个存储器单元的验证编程包括使用第二数据状态的验证操作验证对于第一数据状态的编程。在一个实施例中，一个或多个控制电路还被配置为通过将不同的位线电压施加到不同的存储器单元来感测多个存储器单元中的不同存储单元是否处于不同的数据状态。

5. 再颁专利

USRE46264E1 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：USRE46264E1
公开(公告)日：2017-01-03
申请号：US14290905
申请日：2014-05-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

6. 发明申请

US20150092496A1 Dynamic Bit Line Bias For Programming Non-Volatile Memory 有权
标题翻译：用于编程非易失性存储器的动态位线偏置
公开(公告)号：US20150092496A1
公开(公告)日：2015-04-02
申请号：US14561841
申请日：2014-12-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Ken Oowada , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译：用于一组非易失性存储元件的程序操作。维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。可以使用不同的位线电压，具有公共的步长或不同的步长。结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。在缓慢编程模式下，锁存器保持相关存储元件所经历的程序脉冲计数。当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

7. 发明授权

US08958249B2 Partitioned erase and erase verification in non-volatile memory 有权
标题翻译：在非易失性存储器中分区擦除和擦除验证
公开(公告)号：US08958249B2
公开(公告)日：2015-02-17
申请号：US14195282
申请日：2014-03-03
申请人： SanDisk Technologies Inc.
发明人： Deepanshu Dutta , Chun-Hung Lai , Shih-Chung Lee , Ken Oowada , Masaaki Higashitani
IPC分类号： G11C16/04 , G11C16/14 , G11C16/26 , G11C16/34 , G11C16/16 , G11C11/56
CPC分类号： G11C16/14 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/3427 , G11C16/3445 , G11C16/349
摘要： A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.
摘要翻译：可以通过单独擦除集合的部分来擦除一组存储器单元，以便规范化每个存储器单元的擦除行为并提供更一致的擦除率。擦除电压脉冲可以被施加到存储器单元组，其中第一组单元被偏置用于擦除，而第二组被偏置以阻止擦除。随着设备循环更多，擦除深度变浅。

8. 发明授权

US08942047B2 Bit line current trip point modulation for reading nonvolatile storage elements 有权
标题翻译：用于读取非易失性存储元件的位线电流跳变点调制
公开(公告)号：US08942047B2
公开(公告)日：2015-01-27
申请号：US14290891
申请日：2014-05-29
申请人： Sandisk Technologies Inc.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/06 , G11C16/28 , G11C11/56 , G11C16/26
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译：在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件非易失存储元件超过预定值。

9. 发明授权

US08755234B2 Temperature based compensation during verify operations for non-volatile storage 有权
标题翻译：用于非易失性存储的验证操作期间的温度补偿
公开(公告)号：US08755234B2
公开(公告)日：2014-06-17
申请号：US14048015
申请日：2013-10-07
申请人： Sandisk Technologies Inc.
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C16/26 , G11C16/34 , G11C7/04 , G11C7/12 , G11C16/06
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

10. 发明授权

US09543023B2 Partial block erase for block programming in non-volatile memory 有权
标题翻译：非易失性存储器中块编程的部分块擦除
公开(公告)号：US09543023B2
公开(公告)日：2017-01-10
申请号：US14794236
申请日：2015-07-08
申请人： SanDisk Technologies Inc.
发明人： Chun-hung Lai , Cheng-Kuan Yin , Shih-Chung Lee , Deepanshu Dutta , Ken Oowada
IPC分类号： G11C16/08 , G11C16/16 , G11C16/14 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C16/349 , G11C2211/5648 , G11C2216/24
摘要： A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.
摘要翻译：非易失性存储器系统在编程操作期间利用部分块擦除来减轻编程通过电压干扰的影响。接收与来自块（例如字线的全部或一部分）的一组字线相关联的编程请求。在开始编程之前，系统擦除并软编程块。系统编程用于编程请求的块的字线的子集。在对字线子集编程之后，系统暂停编程操作，并对块的未编程字线执行擦除操作。可以在擦除操作期间禁止已编程的字线和一个或多个可选的缓冲字线擦除。在擦除未编程的字线之后，系统通过对块的未编程区域中剩余的用户数据进行编程来完成编程请求。

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