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1. 发明授权

US09361986B2 High endurance non-volatile storage 有权
标题翻译：高耐久性非易失性存储
公开(公告)号：US09361986B2
公开(公告)日：2016-06-07
申请号：US13622045
申请日：2012-09-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/10 , G11C5/06 , G11C11/56
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

2. 发明授权

US09105349B2 Adaptive operation of three dimensional memory 有权
标题翻译：三维记忆的自适应操作
公开(公告)号：US09105349B2
公开(公告)日：2015-08-11
申请号：US14281404
申请日：2014-05-19
申请人： SanDisk Technologies Inc.
发明人： Chris Avila , Gautam Dusija , Jian Chen , Yingda Dong , Man Mui , Seungpil Lee , Alex Mak
IPC分类号： G11C11/34 , G11C16/34 , G11C29/04 , G06F11/10 , G06F11/14
CPC分类号： G11C16/3404 , G06F11/1048 , G06F11/141 , G06F11/1497 , G11C29/04
摘要： When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.
摘要翻译：当通过误差校正码（ECC）将来自三维NAND存储器阵列的一部分的数据确定为不可校正时，确定在大于该部分的整个单元中ECC是否不可纠正数据。如果修改的读取条件提供ECC可校正数据，则修改的读取条件被记录以用于较大单元的后续读取。

3. 发明授权

US08885416B2 Bit line current trip point modulation for reading nonvolatile storage elements 有权
标题翻译：用于读取非易失性存储元件的位线电流跳变点调制
公开(公告)号：US08885416B2
公开(公告)日：2014-11-11
申请号：US13754852
申请日：2013-01-30
申请人： Sandisk Technologies Inc.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/06 , G11C16/28 , G11C11/56 , G11C16/26
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译：在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件非易失存储元件超过预定值。

4. 发明申请

US20140269100A1 SHARED BIT LINE STRING ARCHITECTURE 有权
标题翻译：共享点行线建筑
公开(公告)号：US20140269100A1
公开(公告)日：2014-09-18
申请号：US13797298
申请日：2013-03-12
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jongsun Sel , Seungpil Lee , Kwang-Ho Kim , Tuan Pham
IPC分类号： G11C16/24
CPC分类号： G11C16/24 , G11C7/12 , G11C7/18 , G11C16/0483 , G11C2207/002
摘要： Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
摘要翻译：描述使用共享位线串结构对存储器单元进行编程和读取的方法。在一些实施例中，存储器单元和选择器件可以对应于包括电荷存储层的晶体管。在一些情况下，电荷存储层可以是导电的（例如，在浮栅器件中使用的多晶硅层）或非导电的（例如，在SONOS器件中使用的氮化硅层）。在一些实施例中，一对串的第一串中的存储器单元的选择可以包括将SEO晶体管设置为导通状态，并将控制漏极侧选择晶体管的SGD线设置为大于第一阈值电压与第一串的第一漏极侧选择晶体管相关联，并且小于与该对串的第二串的第二漏极侧选择晶体管相关联的第二阈值电压。

5. 发明申请

US20140226402A1 Fast-Reading NAND Flash Memory 有权
标题翻译：快速读取NAND闪存
公开(公告)号：US20140226402A1
公开(公告)日：2014-08-14
申请号：US13765349
申请日：2013-02-12
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yacov Duzly , Alon Marcu , Yuval Kenan , Yan Li , Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.
摘要翻译：在闪速存储器中，通过在多页读取期间保持全局字线电压，并且通过同时将旧的所选字线从识别电压转换到读取电压并转换新的选择字，快速连续读取平面中的两页或多页从读取电压到鉴别电压。

6. 发明申请

US20140211568A1 BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS 有权
标题翻译：用于读取非易失性存储元件的位线电流三点调制
公开(公告)号：US20140211568A1
公开(公告)日：2014-07-31
申请号：US13754852
申请日：2013-01-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： Man L. Mui , Teruhiko Kamei , Yingda Dong , Ken Oowada , Yosuke Kato , Fumitoshi Ito , Seungpil Lee
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
摘要翻译：在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件非易失存储元件超过预定值。

7. 发明申请

US20140036601A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：US20140036601A1
公开(公告)日：2014-02-06
申请号：US14048015
申请日：2013-10-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C16/34
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

8. 发明授权

US09318206B2 Selective word line erase in 3D non-volatile memory 有权
标题翻译： 3D非易失性存储器中的选择性字线擦除
公开(公告)号：US09318206B2
公开(公告)日：2016-04-19
申请号：US14536923
申请日：2014-11-10
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C16/14 , G11C16/04 , G11C16/16 , H01L29/792 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.
摘要翻译：用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

9. 发明申请

US20160035430A1 Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced Layout Area and Power Consumption 有权
标题翻译：紧凑型高速感应放大器，用于非易失性存储器，具有减少的布局面积和功耗
公开(公告)号：US20160035430A1
公开(公告)日：2016-02-04
申请号：US14852854
申请日：2015-09-14
申请人： SanDisk Technologies, Inc.
发明人： Man Lung Mui , Jongmin Park , Hao Thai Nguyen , Seungpil Lee
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/067 , G11C11/5642 , G11C16/28 , G11C16/3436
摘要： A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.
摘要翻译：介绍了一种适用于非易失性存储器电路的紧凑且通用的高速读出放大器。感测放大器电路连接到第一和第二电源电平，用于设置位线上的编程禁止电平的第一电平和用于对用于感测操作的位线进行预充电的第二电平。在数据锁存器之外，感测放大器只能使用NMOS晶体管。电路的布置也允许同时对位线进行放电，将感测结果传送到其他锁存器。

10. 发明授权

US09063671B2 Write operations with full sequence programming for defect management in nonvolatile memory 有权
标题翻译：对非易失性存储器中的缺陷管理进行全序列编程的写操作
公开(公告)号：US09063671B2
公开(公告)日：2015-06-23
申请号：US13933987
申请日：2013-07-02
申请人： SanDisk Technologies Inc.
发明人： Chris Nga Yee Avila , Gautam Ashok Dusija , Jian Chen , Alexander Kwok-Tung Mak , Seungpil Lee , Mrinal Kochar , Pao-Ling Koh
IPC分类号： G06F12/00 , G06F3/06 , G06F12/02
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/065 , G06F12/0246 , G11C11/5628 , G11C2211/5641
摘要： Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. High error rate format may be MLC format and programming in the high error rate format may program both lower page and upper page data together in a full sequence programming scheme that is suitable for handling high data volume.
摘要翻译：在非易失性存储器中以较高错误率格式存储的数据以较低的错误率格式进行备份。要被存储的数据可以被传送到片上数据锁存器，其中它被维护，同时以高错误率格式和低错误率格式被编程，而不重新发送到非易失性存储器。高错误率格式可以是MLC格式，并且以高错误率格式的编程可以以适合于处理高数据量的全序列编程方案将低页面和高位页数据一起编程。

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