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1. 发明授权

US09030895B2 Memory device with pin register to set input/output direction and bitwidth of data signals 有权
标题翻译：具有引脚寄存器的存储器件，用于设置数据信号的输入/输出方向和位宽
公开(公告)号：US09030895B2
公开(公告)日：2015-05-12
申请号：US12510633
申请日：2009-07-28
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko , Akira Yabu
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko , Akira Yabu
IPC分类号： G11C7/00 , G06F13/42
CPC分类号： G06F13/4217
摘要： A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use.
摘要翻译：随机存取存储器包括数据信号线，用于当数据被发送到数据信号线时提供同步信号的数据同步信号的数据同步信号线以及设置模块。设置模块确定数据信号线是否被设置为用于公共输入/输出使用的数据信号线，仅用于输出的数据信号线或仅用于输入的数据信号线，并且还确定是否数据同步信号线被设置为用于公共输入/输出使用的数据同步信号线，仅用于输出的数据同步信号线或仅用于输入的数据同步信号线。

2. 发明申请

US20100131724A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100131724A1
公开(公告)日：2010-05-27
申请号：US12597097
申请日：2008-04-25
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00 , G11C7/00 , G11C8/16
CPC分类号： G11C14/00 , G06F13/4243 , G11C16/30
摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
摘要翻译：本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

3. 发明授权

US08886893B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08886893B2
公开(公告)日：2014-11-11
申请号：US12597097
申请日：2008-04-25
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00 , G11C7/00 , G06F13/42
CPC分类号： G11C14/00 , G06F13/4243 , G11C16/30
摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
摘要翻译：本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

4. 发明申请

US20070271409A1 MEMORY MODULE, MEMORY SYSTEM, AND DATA PROCESSING SYSTEM 审中-公开
标题翻译：存储器模块，存储器系统和数据处理系统
公开(公告)号：US20070271409A1
公开(公告)日：2007-11-22
申请号：US11748936
申请日：2007-05-15
申请人： Seiji Miura , Akira Yabu , Yoshinori Haraguchi
发明人： Seiji Miura , Akira Yabu , Yoshinori Haraguchi
IPC分类号： G06F12/06
CPC分类号： G06F12/0623 , Y02D10/13
摘要： A user-friendly data processing system apparatus which ensures the expandability of memory capacity and high speed processing with low cost is provided. The data processing system is composed of a data processing unit, a volatile memory and a nonvolatile memory. The data processing unit, the volatile memory and the nonvolatile memory are connected in series and by reducing the number of connection signals fast processing is realized while maintaining the memory capacity expandability. Upon transferring a data of the nonvolatile memory to the volatile memory, an error correction is executed, therefore, the reliability is improved. The data processing system composed of the plurality of memory chips is formed as a data processing system module in which the each chips are stacked and arranged, and wiring is formed by ball grid array (BGA) and bonding between the chips.
摘要翻译：提供一种用户友好的数据处理系统装置，其确保存储容量的可扩展性和低成本的高速处理。数据处理系统由数据处理单元，易失性存储器和非易失性存储器组成。数据处理单元，易失性存储器和非易失性存储器被串联连接，并且通过减少在保持存储器容量扩展性的同时实现快速处理的连接信号的数量。在将非易失性存储器的数据传送到易失性存储器时，执行错误校正，因此提高了可靠性。由多个存储器芯片组成的数据处理系统形成为数据处理系统模块，其中每个芯片被堆叠和布置，并且布线由球栅阵列（BGA）形成并且芯片之间的结合。

5. 发明授权

US08271740B2 Multiport memory and information processing system 有权
标题翻译：多端口内存和信息处理系统
公开(公告)号：US08271740B2
公开(公告)日：2012-09-18
申请号：US12411974
申请日：2009-03-26
申请人： Seiji Miura , Yoshinori Matsui , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Matsui , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1663
摘要： In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.
摘要翻译：在信息处理系统中，多个信息处理装置CHIP0和CHIP1连接到具有多个端口的多端口存储器MPMEM0，并且多端口存储器MPMEM0中的存储区域可以被改变为由特定端口和存储区域所占用的存储区域多个端口。在这样的时刻，在从端口发出请求之后，可以从其他端口提供该请求的状态。

6. 发明申请

US20150213889A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150213889A1
公开(公告)日：2015-07-30
申请号：US14415706
申请日：2012-07-19
申请人： Seiji Miura , Hiroshi Uchigaito , Kenzo Kurotsuchi
发明人： Seiji Miura , Hiroshi Uchigaito , Kenzo Kurotsuchi
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F12/0246 , G06F2212/1008 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/0483 , G11C29/24 , G11C2029/0411 , G11C2213/72 , G11C2213/74 , G11C2213/75
摘要： A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.
摘要翻译：包括非易失性存储单元的半导体器件实现了可靠性和便利性的提高。半导体器件包括包括多个可重写存储单元（CL）的非易失性存储器单元和控制对非易失性存储器单元的访问的控制电路。例如，控制电路将一个物理地址分配给非易失性存储器单元中的链式存储器阵列CY。控制电路根据关于物理地址的第一写入命令，对链存储器阵列CY的分开的存储单元（例如CL0）进行写入，并对存储单元（例如CL1）进行写入，这是根据关于物理地址的第二写命令的另一部分。

7. 发明授权

US08255622B2 Memory controller and data processing system 有权
标题翻译：内存控制器和数据处理系统
公开(公告)号：US08255622B2
公开(公告)日：2012-08-28
申请号：US13233308
申请日：2011-09-15
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/0215 , G11C7/1018 , Y02D10/13 , Y02D10/14
摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
摘要翻译：存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问在高速和低功耗下。

8. 发明申请

US20120134203A1 Semiconductor Device and Data Processing System 有权
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20120134203A1
公开(公告)日：2012-05-31
申请号：US13300139
申请日：2011-11-18
申请人： Seiji Miura , Satoru Hanzawa
发明人： Seiji Miura , Satoru Hanzawa
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C13/0007 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2211/5623
摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.
摘要翻译：在相变存储器中，当写入M位（8位= 1字节）数据时，以n位（M> n）数据为单位执行擦除操作和编程操作。此外，当写入M位数据时，以n位（M> n）数据为单位执行编程操作。此外，当从存储单元读取M位数据时，以n位（M> n）数据为单位执行读操作。例如，当数据被写入相变存储器时，数据不被重写，而是在擦除目标存储单元之后执行程序。擦除的数据大小和程序的数据大小相等。擦除和编程操作仅针对所需的数据大小执行。

9. 发明申请

US20120004305A1 EXTERNAL PREPARATION CONTAINING ANALGESIC/ANTI-INFLAMMATORY AGENT 审中-公开
标题翻译：含有毒性/抗炎药的外用制剂
公开(公告)号：US20120004305A1
公开(公告)日：2012-01-05
申请号：US13256024
申请日：2010-03-11
申请人： Seiji Miura , Makoto Kanebako
发明人： Seiji Miura , Makoto Kanebako
IPC分类号： A61K31/196 , A61P29/00 , A61K47/44 , A61K47/08 , A61K47/10
CPC分类号： A61K31/045 , A61K9/0014 , A61K9/7053 , A61K31/196 , A61K45/06 , A61K47/08 , A61K47/10 , A61K47/44 , A61K2300/00
摘要： An external preparation containing the following components (A), (B), (C), and (D): (A) a non-steroidal analgesic/anti-inflammatory agent, (B) a terpene and/or an essential oil containing a terpene, (C) a higher alcohol, and (D) a polyoxyalkylene alkyl ether and/or a polyoxyalkylene alkenyl ether. The external preparation of the present invention has improved skin permeation, and can thus be effective at a low concentration, and also has excellent appearance.
摘要翻译：含有以下组分（A），（B），（C）和（D）的外用制剂：（A）非甾体止痛/消炎剂，（B）萜烯和/或含有萜烯，（C）高级醇，和（D）聚氧化烯烷基醚和/或聚氧化烯链烯基醚。本发明的外用制剂具有改善的皮肤渗透性，因此能够以低浓度有效，外观也优异。

10. 发明授权

US07613880B2 Memory module, memory system, and information device 有权
标题翻译：内存模块，内存系统和信息设备
公开(公告)号：US07613880B2
公开(公告)日：2009-11-03
申请号：US10536460
申请日：2003-11-27
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F12/00
CPC分类号： G11C11/005 , G06F12/0638 , G06F2212/2022 , G11C7/20 , G11C11/4072 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.
摘要翻译：提供了包括大容量ROM和RAM的存储器系统，其中启用了高速读写。配置包括非易失性存储器（CHIP1），DRAM（CHIP3），控制电路（CHIP2）和信息处理设备（CHIP4））的存储器系统。 FLASH中的数据提前传输到SRAM或DRAM，以加快速度。在非易失性存储器（FLASH）和DRAM（CHIP3）之间的数据传输可以在后台执行。包括这些多个芯片的存储器系统被配置为存储器系统模块，其中每个芯片相互层叠，并且每个芯片经由球栅阵列（BGA）和芯片之间的接合线布线。 FLASH中的数据可以通过保护FLASH中的数据可以在DRAM中复制的区域以及在接通电源或通过加载指令之后将数据传送到DRAM中，以与DRAM类似的速度读取速度。

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