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1. 发明授权

US09030895B2 Memory device with pin register to set input/output direction and bitwidth of data signals 有权
标题翻译：具有引脚寄存器的存储器件，用于设置数据信号的输入/输出方向和位宽
公开(公告)号：US09030895B2
公开(公告)日：2015-05-12
申请号：US12510633
申请日：2009-07-28
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko , Akira Yabu
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko , Akira Yabu
IPC分类号： G11C7/00 , G06F13/42
CPC分类号： G06F13/4217
摘要： A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use.
摘要翻译：随机存取存储器包括数据信号线，用于当数据被发送到数据信号线时提供同步信号的数据同步信号的数据同步信号线以及设置模块。设置模块确定数据信号线是否被设置为用于公共输入/输出使用的数据信号线，仅用于输出的数据信号线或仅用于输入的数据信号线，并且还确定是否数据同步信号线被设置为用于公共输入/输出使用的数据同步信号线，仅用于输出的数据同步信号线或仅用于输入的数据同步信号线。

2. 发明授权

US08886893B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08886893B2
公开(公告)日：2014-11-11
申请号：US12597097
申请日：2008-04-25
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00 , G11C7/00 , G06F13/42
CPC分类号： G11C14/00 , G06F13/4243 , G11C16/30
摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
摘要翻译：本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

3. 发明申请

US20100131724A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100131724A1
公开(公告)日：2010-05-27
申请号：US12597097
申请日：2008-04-25
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00 , G11C7/00 , G11C8/16
CPC分类号： G11C14/00 , G06F13/4243 , G11C16/30
摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
摘要翻译：本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

4. 发明申请

US20070271409A1 MEMORY MODULE, MEMORY SYSTEM, AND DATA PROCESSING SYSTEM 审中-公开
标题翻译：存储器模块，存储器系统和数据处理系统
公开(公告)号：US20070271409A1
公开(公告)日：2007-11-22
申请号：US11748936
申请日：2007-05-15
申请人： Seiji Miura , Akira Yabu , Yoshinori Haraguchi
发明人： Seiji Miura , Akira Yabu , Yoshinori Haraguchi
IPC分类号： G06F12/06
CPC分类号： G06F12/0623 , Y02D10/13
摘要： A user-friendly data processing system apparatus which ensures the expandability of memory capacity and high speed processing with low cost is provided. The data processing system is composed of a data processing unit, a volatile memory and a nonvolatile memory. The data processing unit, the volatile memory and the nonvolatile memory are connected in series and by reducing the number of connection signals fast processing is realized while maintaining the memory capacity expandability. Upon transferring a data of the nonvolatile memory to the volatile memory, an error correction is executed, therefore, the reliability is improved. The data processing system composed of the plurality of memory chips is formed as a data processing system module in which the each chips are stacked and arranged, and wiring is formed by ball grid array (BGA) and bonding between the chips.
摘要翻译：提供一种用户友好的数据处理系统装置，其确保存储容量的可扩展性和低成本的高速处理。数据处理系统由数据处理单元，易失性存储器和非易失性存储器组成。数据处理单元，易失性存储器和非易失性存储器被串联连接，并且通过减少在保持存储器容量扩展性的同时实现快速处理的连接信号的数量。在将非易失性存储器的数据传送到易失性存储器时，执行错误校正，因此提高了可靠性。由多个存储器芯片组成的数据处理系统形成为数据处理系统模块，其中每个芯片被堆叠和布置，并且布线由球栅阵列（BGA）形成并且芯片之间的结合。

5. 发明申请

US20090003026A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090003026A1
公开(公告)日：2009-01-01
申请号：US12137802
申请日：2008-06-12
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C5/02 , G11C8/00
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.
摘要翻译：半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。在芯片的中心区域，IO线的布线区域减小。

6. 发明授权

US07864618B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07864618B2
公开(公告)日：2011-01-04
申请号：US12137802
申请日：2008-06-12
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C8/00
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.
摘要翻译：半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。在芯片的中心区域，IO线的布线区域减小。

7. 发明申请

US20060133123A1 Semiconductor memory device and method of making design change to semiconductor chip 有权
标题翻译：半导体存储器件及其制造方法改为半导体芯片
公开(公告)号：US20060133123A1
公开(公告)日：2006-06-22
申请号：US11302325
申请日：2005-12-14
申请人： Yoshinori Haraguchi
发明人： Yoshinori Haraguchi
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/1057
摘要： The positions of the main driver 10, the output pad 20 and the first buffer 61 and the second buffer 62 are changed from the central region 111 to the peripheral region 120, and the first control signal line 31 and the second control signal line 32 are elongated. The distance between the output pad 20 and the main driver 10 is maintained so that the resistance between the output pad 20 and the main driver 10 does not increase.
摘要翻译：主驱动器10，输出焊盘20以及第一缓冲器61和第二缓冲器62的位置从中心区域111改变为周边区域120，第一控制信号线31和第二控制信号线32 细长保持输出焊盘20和主驱动器10之间的距离，使得输出焊盘20和主驱动器10之间的电阻不增加。

8. 发明授权

US07796453B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07796453B2
公开(公告)日：2010-09-14
申请号：US12145240
申请日：2008-06-24
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C11/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069
摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.
摘要翻译：半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。

9. 发明授权

US6034907A Semiconductor integrated circuit device with built-in test circuit for applying stress to timing generator in burn-in test 有权
标题翻译：具有内置测试电路的半导体集成电路器件，用于在老化测试中对定时发生器施加应力
公开(公告)号：US6034907A
公开(公告)日：2000-03-07
申请号：US273561
申请日：1999-03-22
申请人： Yoshinori Haraguchi
发明人： Yoshinori Haraguchi
IPC分类号： G01R31/28 , G06F11/22 , G11C29/02 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C29/02
摘要： A semiconductor memory device has a device identification code to see whether or not a packet signal is addressed thereto, and a timing generator starts a control sequence for a data access in response to a hit signal representative of the consistency between the stored device identification code and an input device identification code incorporated in the packet signal, wherein a signal receiving circuit is shared between the packet signal and a test signal representative of instructions for burn-in test, and a logic gate is provided for directly generating the hit signal from an internal mode signal representative of the test mode so that the timing generator starts the control sequence in the burn-in test regardless of the consistency between the test signal and the stored device identification code.
摘要翻译：半导体存储器件具有用于查看分组信号是否寻址到其中的器件识别码，并且定时发生器响应于表示存储的器件识别码和存储器件识别码之间的一致性的命中信号而启动用于数据访问的控制序列包含在分组信号中的输入装置识别码，其中在分组信号和表示用于老化测试的指令的测试信号之间共享信号接收电路，并且提供逻辑门，用于从内部直接产生命中信号模式信号表示测试模式，使得定时发生器启动老化测试中的控制序列，而不管测试信号和存储的设备识别码之间的一致性。

10. 发明授权

US07280380B2 Semiconductor memory device and method of making design change to semiconductor chip 有权
标题翻译：半导体存储器件及其制造方法改为半导体芯片
公开(公告)号：US07280380B2
公开(公告)日：2007-10-09
申请号：US11302325
申请日：2005-12-14
申请人： Yoshinori Haraguchi
发明人： Yoshinori Haraguchi
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/1057
摘要： The positions of the main driver 10, the output pad 20 and the first buffer 61 and the second buffer 62 are changed from the central region 111 to the peripheral region 120, and the first control signal line 31 and the second control signal line 32 are elongated. The distance between the output pad 20 and the main driver 10 is maintained so that the resistance between the output pad 20 and the main driver 10 does not increase.
摘要翻译：主驱动器10，输出焊盘20以及第一缓冲器61和第二缓冲器62的位置从中心区域111改变为周边区域120，第一控制信号线31和第二控制信号线32 细长保持输出焊盘20和主驱动器10之间的距离，使得输出焊盘20和主驱动器10之间的电阻不增加。

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