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1. 发明授权

US11133812B1 Asynchronous SAR ADC using two-stage comparator having separate resets 有权
公开(公告)号：US11133812B1
公开(公告)日：2021-09-28
申请号：US17080263
申请日：2020-10-26
申请人： Semyon Lebedev , Babak Zamanlooy , Marc-Andre Lacroix
发明人： Semyon Lebedev , Babak Zamanlooy , Marc-Andre Lacroix
IPC分类号： H03M1/06 , H03M1/46 , H03M1/40 , H03M1/38 , H03M1/12
摘要： Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.

2. 发明授权

US10776234B2 On-die input capacitive divider for wireline receivers with integrated loopback 有权
公开(公告)号：US10776234B2
公开(公告)日：2020-09-15
申请号：US16183912
申请日：2018-11-08
申请人： Marc-Andre Lacroix
发明人： Marc-Andre Lacroix
IPC分类号： G06F11/00 , G06F11/263 , G06F11/22 , H04B1/40
摘要： There is provided an integrated loopback used for on-die self-test and diagnosis of transceiver faults. According to embodiments, there is provided an interface network including an AC coupling capacitor interposed between input pins of the interface network and an input of an amplifier, a shunt capacitor interposed between the AC coupling capacitor and the input of the amplifier and a selector. The selector includes a mission mode circuit component connected to a bottom plate of the shunt capacitor and the selector is configured to select between a first mode and a second mode, wherein the first mode is mission mode and the second mode is loopback mode, wherein in the second mode the mission mode circuit component forms at least part of a circuit that supplies a loopback signal.

3. 发明授权

US10103743B1 Analog-to-digital converter and control method thereof 有权
公开(公告)号：US10103743B1
公开(公告)日：2018-10-16
申请号：US15808095
申请日：2017-11-09
申请人： Luke Wang , Anthony Chan Carusone , Marc-Andre Lacroix
发明人： Luke Wang , Anthony Chan Carusone , Marc-Andre Lacroix
IPC分类号： H03M3/00 , H03M1/16 , H03M1/12 , H03M1/08 , H03H17/02
摘要： The present disclosure relates to an analog-to-digital converter (ADC) and a method for controlling an ADC. The ADC includes a plurality of quantization levels for analog-to-digital conversion. The ADC is adapted for utilizing a subset of the plurality of quantization levels for analog-to-digital signal conversion. The subset is formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level. The method includes using a subset of the plurality of quantization levels for analog-to-digital signal conversion, the subset being formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level.

4. 发明授权

US09553600B1 Skew detection and correction in time-interleaved analog-to-digital converters 有权
标题翻译：时间交错模数转换器中的偏斜检测和校正
公开(公告)号：US09553600B1
公开(公告)日：2017-01-24
申请号：US15187161
申请日：2016-06-20
申请人： Marc-Andre Lacroix , Henry Wong , Davide Tonietto
发明人： Marc-Andre Lacroix , Henry Wong , Davide Tonietto
IPC分类号： H03M1/06 , H03M1/12 , H03M1/00 , H04L7/00
CPC分类号： H03M1/0624 , G06F1/10 , H03M1/00 , H03M1/12 , H03M1/1215 , H03M1/1225 , H04L7/0008
摘要： The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.
摘要翻译：本公开提供了一种用于校正时间交织的模数转换器中的时钟偏移的系统，电路和方法。沿相应的通道接收至少两个时钟信号。通过对通道应用一个或多个第一调整因子直到第一时钟信号的边沿与参考信号的转换点对准来考虑承载第一时钟信号的第一通道的延迟。第一个时钟信号被交换到第二个信道，反之亦然。将由第一时钟信号采样的参考信号的值与由第二时钟信号采样的参考信号的值进行比较，以确定第二信道相对于第一信道的偏斜，以及一个或多个第二信道基于确定的第二通道的倾斜度，将调整因子应用于第二通道。

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