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1. 发明授权

US08275560B2 Power measurement techniques of a system-on-chip (SOC) 有权
标题翻译：片上系统（SOC）的功率测量技术
公开(公告)号：US08275560B2
公开(公告)日：2012-09-25
申请号：US12557263
申请日：2009-09-10
申请人： Sivakumar Radhakrishnan , Sin S. Tan , Stephan J. Jourdan , Lily P. Looi , Yi-Feng Liu
发明人： Sivakumar Radhakrishnan , Sin S. Tan , Stephan J. Jourdan , Lily P. Looi , Yi-Feng Liu
IPC分类号： G01R15/00 , G01R19/00 , G01R21/00 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
摘要翻译：一种能够以各种模式对片上系统进行功率测量的方法和系统。在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。这允许钩子或接口在外部访问片上系统进行测量。例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量，片上片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。另外，由于易于检测故障部件，所以能够提高SOC的整体产量。

2. 发明申请

US20110060931A1 POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC) 有权
标题翻译：系统芯片（SOC）的功率测量技术
公开(公告)号：US20110060931A1
公开(公告)日：2011-03-10
申请号：US12557263
申请日：2009-09-10
申请人： SIVAKUMAR RADHAKRISHNAN , Sin S. Tan , Stephan J. Jourdan , Lily P. Lool , Yi-Feng Liu
发明人： SIVAKUMAR RADHAKRISHNAN , Sin S. Tan , Stephan J. Jourdan , Lily P. Lool , Yi-Feng Liu
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
摘要翻译：一种能够以各种模式对片上系统进行功率测量的方法和系统。在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。这允许钩子或接口在外部访问片上系统进行测量。例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量，片上片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。另外，由于易于检测故障部件，所以能够提高SOC的整体产量。

3. 发明授权

US08782456B2 Dynamic and idle power reduction sequence using recombinant clock and power gating 有权
标题翻译：使用重组时钟和电源门控的动态和空闲功率降低序列
公开(公告)号：US08782456B2
公开(公告)日：2014-07-15
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

4. 发明申请

US20110296222A1 DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING 有权
标题翻译：使用重构时钟和功率增益的动态和空闲功率降低序列
公开(公告)号：US20110296222A1
公开(公告)日：2011-12-01
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

5. 发明授权

US06622215B2 Mechanism for handling conflicts in a multi-node computer architecture 失效
公开(公告)号：US06622215B2
公开(公告)日：2003-09-16
申请号：US09753263
申请日：2000-12-29
申请人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Sin S. Tan
发明人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Sin S. Tan
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F12/0813 , G06F12/082 , G06F12/0831
摘要： According to one embodiment, a method is disclosed. The method includes receiving a first request from a first node in a multi-node computer system to invalidate a first cache line at a second node. The method also includes receiving a second request from the second node to invalidate the first cache line at the first node and detecting the concurrent requests at conflict detection circuitry.

6. 发明授权

US08850250B2 Integration of processor and input/output hub 有权
标题翻译：处理器和输入/输出集线器的集成
公开(公告)号：US08850250B2
公开(公告)日：2014-09-30
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

7. 发明申请

US20110296216A1 INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB 有权
标题翻译：处理器和输入/输出总线的集成
公开(公告)号：US20110296216A1
公开(公告)日：2011-12-01
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

8. 发明授权

US09417821B2 Presentation of direct accessed storage under a logical drive model 有权
标题翻译：在逻辑驱动器模型下呈现直接访问存储
公开(公告)号：US09417821B2
公开(公告)日：2016-08-16
申请号：US13976262
申请日：2011-09-30
申请人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
发明人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
IPC分类号： G06F3/06 , G06F13/28 , G06F11/10 , G06F12/08
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0613 , G06F3/0619 , G06F3/0626 , G06F3/064 , G06F3/0646 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F11/1068 , G06F12/0866 , G06F13/102 , G06F13/1668 , G06F13/4068 , G06F13/4282 , G06F2212/262 , G06F2213/0026 , G06F2213/0032
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
摘要翻译：根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。

9. 发明授权

US07500029B2 Maximal length packets 有权
标题翻译：最大长度数据包
公开(公告)号：US07500029B2
公开(公告)日：2009-03-03
申请号：US10977230
申请日：2004-10-29
申请人： Sivakumar Radhakrishnan , Siva Balasubramanian , Sin S. Tan , Suneeta Sah
发明人： Sivakumar Radhakrishnan , Siva Balasubramanian , Sin S. Tan , Suneeta Sah
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.
摘要翻译：本文阐述了检测和刷新最大长度数据包。在一个实施例中，该方法包括接收冲洗事件，并且响应于冲洗事件，重复地从写入组合存储区域检测写入数据的最大长度分组，并将检测到的最大长度分组刷新到目标输入/输出（I / O）设备。每个最大长度分组是写入数据的最大有效载荷的分组，其可以在遵守用于总线的分组协议规则的情况下在写入组合存储区域中被表达。

10. 发明申请

US20140082451A1 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC 审中-公开
标题翻译：有效和可扩展的循环冗余使用GALOIS-FIELD ARTIMETIC检查电路
公开(公告)号：US20140082451A1
公开(公告)日：2014-03-20
申请号：US14083059
申请日：2013-11-18
申请人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
发明人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1076 , H03M1/1052 , H03M7/42 , H03M13/09 , H03M13/091 , H03M13/158 , H03M13/6575
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
摘要翻译：本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

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