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1. 发明授权

US11616631B2 Integrated circuit with radio frequency interconnect 有权
公开(公告)号：US11616631B2
公开(公告)日：2023-03-28
申请号：US15931273
申请日：2020-05-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Huan-Neng Chen , William Wu Shen , Chewn-Pu Jou , Feng Wei Kuo , Lan-Chou Cho , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
IPC分类号： H04J3/00 , H04L5/14 , H04W52/02
摘要： An integrated circuit includes a first through fourth devices positioned over a substrate, the first device including first through third transceivers, the second device including a fourth transceiver, the third device including a fifth transceiver, and the fourth device including a sixth transceiver. A first radio frequency interconnect (RFI) includes the first transceiver coupled to the fourth transceiver through a first guided transmission medium, a second RFI includes the second transceiver coupled to the fifth transceiver through a second guided transmission medium, and a third RFI includes the third transceiver coupled to the sixth transceiver by the second guided transmission medium.

2. 发明授权

US11387683B2 Composite integrated circuits and methods for wireless interactions therewith 有权
公开(公告)号：US11387683B2
公开(公告)日：2022-07-12
申请号：US17015602
申请日：2020-09-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Min-Jer Wang , Ching-Nen Peng , Chewn-Pu Jou , Feng Wei Kuo , Hao Chen , Hung-Chih Lin , Huan-Neng Chen , Kuang-Kai Yen , Ming-Chieh Liu , Tsung-Hsiung Lee
IPC分类号： G01R31/28 , H02J50/40 , H01L25/065 , H01L23/538 , H02J50/10 , H02J50/80 , G01R31/302 , H01L23/544 , G06F30/39 , H02J50/20 , H01L23/00
摘要： An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

3. 发明授权

US10938443B2 Communication system and method of data communications 有权
公开(公告)号：US10938443B2
公开(公告)日：2021-03-02
申请号：US16773448
申请日：2020-01-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Feng Wei Kuo , William Wu Shen , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho
IPC分类号： H04B3/04 , H03H7/01 , H03G5/28 , H04L27/22 , H03G3/30 , H03H11/04 , H04L27/38 , H04B17/21 , H04B1/00 , H04B1/10
摘要： A communication system includes a modulator configured to generate a modulated signal responsive to at least a data signal, and a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter configured to generate a filtered first signal based on a first signal, and a gain adjusting circuit coupled to the filter. The first signal is based on the first carrier signal and modulated signal. The filter has a gain controlled by a set of control signals. The gain adjusting circuit is configured to adjust the gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.

4. 发明授权

US10659092B2 Channel loss compensation circuits 有权
公开(公告)号：US10659092B2
公开(公告)日：2020-05-19
申请号：US16399811
申请日：2019-04-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Lan-Chou Cho , Chewn-Pu Jou , Feng Wei Kuo , Huan-Neng Chen , William Wu Shen
IPC分类号： H04B1/10 , H04B1/04 , H04L25/02 , H01L23/66 , H04L25/03
摘要： A receiver circuit includes a plurality of receivers, each of the receivers being associated with a carrier of a plurality of carriers, and a decoupler configured to receive a transmission signal from a transmission channel and output a plurality of divided transmission signals to the plurality of receivers. An equalizer is configured to modify either the transmission signal or one of the divided transmission signals.

5. 发明授权

US10148378B2 PLL for carrier generator and method of generating carrier signals 有权
公开(公告)号：US10148378B2
公开(公告)日：2018-12-04
申请号：US15655497
申请日：2017-07-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , William Wu Shen
IPC分类号： H04J3/06 , H03L7/099 , H04L7/00 , H04L7/033 , H04L7/04 , H03L7/18 , H04L27/00 , H04L27/26
摘要： A phase locked loop (PLL) for a carrier generator includes a front-end circuit that receives a frequency reference signal and generates a control signal based on the frequency reference signal and a feedback signal. A demultiplexer selectively outputs the control signal to a plurality of tuning arrangements. The plurality of tuning arrangements includes a first tuning arrangement that generates a first carrier signal based on the control signal and a second tuning arrangement that generates a second carrier signal based on the control signal. A multiplexer outputs the feedback signal based on the first carrier signal and the second carrier signal.

6. 发明授权

US10056939B2 Communication system and method of data communications 有权
公开(公告)号：US10056939B2
公开(公告)日：2018-08-21
申请号：US15704140
申请日：2017-09-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Feng Wei Kuo , William Wu Shen , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho
IPC分类号： H04L27/02 , H04B3/04 , H03G3/30 , H03H11/04 , H04L27/38 , H04B17/21 , H04B1/00 , H04B1/10
CPC分类号： H04B3/04 , H03G3/3068 , H03G3/3078 , H03G5/28 , H03H7/0115 , H03H7/0153 , H03H11/0405 , H04B1/005 , H04B1/10 , H04B17/21 , H04L27/22 , H04L27/38
摘要： A communication system includes a demodulator configured to demodulate a modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a gain adjusted based on a set of control signals. The gain adjusting circuit is coupled to the filter, and is configured to generate the set of control signals based on at least a voltage of the filtered first signal. The gain adjusting circuit includes a first peak detector coupled to the filter. The first peak detector is configured to output a peak value of the voltage of the filtered first signal.

7. 发明申请

US20170257064A1 Semiconductor Device and Method 审中-公开
公开(公告)号：US20170257064A1
公开(公告)日：2017-09-07
申请号：US15599694
申请日：2017-05-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Lan-Chou Cho , Huan-Neng Chen , Chewn-Pu Jou , Feng Wei Kuo
IPC分类号： H03L7/00 , H01F38/14 , H01F5/04 , H03B5/12 , H01F27/28
CPC分类号： H03B5/1243 , H01F5/04 , H01F19/04 , H01F27/2804 , H01F27/2871 , H01F27/288 , H01F38/14 , H03B5/1212 , H03B5/1228 , H03B5/1256 , H03B5/1265 , H03B5/1296 , H03J2200/10 , H03L7/00 , H03L7/099 , H03L7/0995
摘要： A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew.

8. 发明授权

US09735904B2 PLL with clock and data recovery function for receiver phase synchronization 有权
公开(公告)号：US09735904B2
公开(公告)日：2017-08-15
申请号：US14969295
申请日：2015-12-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Willaim Wu Shen
IPC分类号： H03D3/24 , H04J3/06 , H03L7/099 , H04L7/04 , H04L7/033 , H04L7/00
CPC分类号： H04J3/0658 , H03L7/099 , H03L7/0991 , H03L7/18 , H03L2207/50 , H04L7/0087 , H04L7/0331 , H04L7/04 , H04L27/0014 , H04L27/2637 , H04L27/2657
摘要： A transmitter for a radio frequency interconnect (RFI) includes a carrier generator configured to generate a clock recovery signal, and to transmit the clock recovery signal to a receiver. The carrier generator includes a first tuning arrangement configured to receive a first signal and to generate a first carrier signal based on the first signal. The carrier generator includes a second tuning arrangement configured to receive a second signal different from the first signal, and to generate a second carrier signal based on the second signal. The transmitter includes a first modulator configured to generate a first modulated data signal. The transmitter further includes a second modulator configured to generate a second modulated data signal. The transmitter includes an output configured to selectively transmit the first modulated data signal and the second modulated data signal to the receiver.

9. 发明授权

US09559733B1 Communication system and method of data communications 有权
标题翻译：通信系统和数据通信方法
公开(公告)号：US09559733B1
公开(公告)日：2017-01-31
申请号：US14927783
申请日：2015-10-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY., LTD.
发明人： Feng Wei Kuo , William Wu Shen , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho
IPC分类号： H04B1/10 , H04B1/16
CPC分类号： H04B1/1027 , H04B2001/1054 , H04W4/80 , H04W84/12
摘要： A communication system includes a carrier generator configured to generate a first carrier signal and a demodulator configured to demodulate a modulated signal responsive to the first carrier signal. The demodulator includes a filter and a bandwidth adjusting circuit. The filter is configured to filter a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a first cutoff frequency and a bandwidth. The bandwidth of the filter is controlled by a set of control signals. The bandwidth adjusting circuit is configured to adjust the bandwidth of the filter based on a frequency of the filtered first signal and a frequency of the first signal, or a phase of the filtered first signal and a phase of the first signal. The bandwidth adjusting circuit is configured to generate the set of control signals.
摘要翻译：通信系统包括被配置为产生第一载波信号的载波发生器和被配置为响应于第一载波信号来解调调制信号的解调器。解调器包括滤波器和带宽调整电路。过滤器被配置为过滤第一个信号。第一信号是第一载波信号和调制信号的乘积。滤波器具有第一截止频率和带宽。滤波器的带宽由一组控制信号控制。带宽调整电路被配置为基于滤波的第一信号的频率和第一信号的频率，或滤波的第一信号的相位和第一信号的相位来调整滤波器的带宽。带宽调整电路被配置为产生一组控制信号。

10. 发明授权

US09374038B2 Phase frequency detector circuit 有权
标题翻译：相位检波电路
公开(公告)号：US09374038B2
公开(公告)日：2016-06-21
申请号：US14133982
申请日：2013-12-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D13/00 , H03L7/087 , H03L7/089 , H03L7/10
CPC分类号： H03D13/00 , H03D13/004 , H03L7/087 , H03L7/089 , H03L7/10
摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.
摘要翻译：相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。边缘检测器电路被配置为接收第一输入信号和第二输入信号。判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

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