专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07935542B2 Manufacturing method of semiconductor device having memory element with protective film 失效
标题翻译：具有保护膜的存储元件的半导体器件的制造方法
公开(公告)号：US07935542B2
公开(公告)日：2011-05-03
申请号：US12411665
申请日：2009-03-26
申请人： Tatsunori Murata , Mikio Tsujiuchi , Ryoji Matsuda
发明人： Tatsunori Murata , Mikio Tsujiuchi , Ryoji Matsuda
IPC分类号： H01L21/00
CPC分类号： H01L27/228 , G11C11/16
摘要： To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH3 but composed of SiH4/N2/helium (He). The film forming temperature is set at from 200 to 350° C. More ideally, a flow rate ratio of He to SiH4 is set at from 100 to 125.
摘要翻译：为了提供能够形成具有良好绝缘性能的氮化硅膜作为MTJ元件的保护膜的半导体器件的制造方法，而不会劣化MTJ元件的性能。本发明的方法包括以下步骤：在使用平板等离子体CVD装置作为成膜装置的同时，在包括MTJ元件部分（MTJ元件和上电极）的整个表面上形成氮化硅膜，以及不含 NH3，但由SiH4 / N2 /氦（He）组成。成膜温度设定在200〜350℃。更理想的是，将He与SiH4的流量比设定为100〜125。

2. 发明授权

US07772662B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07772662B2
公开(公告)日：2010-08-10
申请号：US12424982
申请日：2009-04-16
申请人： Tatsunori Murata , Mikio Tsujiuchi
发明人： Tatsunori Murata , Mikio Tsujiuchi
IPC分类号： H01L29/82
CPC分类号： H01L27/224 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F41/302 , H01F41/307 , H01L43/08 , H01L43/12
摘要： The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.
摘要翻译：本发明使得可以获得：能够形成高可靠性的上线而不会对MTJ装置的磁性材料的性质产生有害影响的半导体器件; 及其制造方法。使用可还原NH3或H2作为预处理进行等离子体处理。此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 并且成膜温度设定在200℃至350℃的范围内。

3. 发明申请

US20110101431A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110101431A1
公开(公告)日：2011-05-05
申请号：US12911558
申请日：2010-10-25
申请人： Yosuke TAKEUCHI , Mikio Tsujiuchi , Tatsunori Murata
发明人： Yosuke TAKEUCHI , Mikio Tsujiuchi , Tatsunori Murata
IPC分类号： H01L29/82 , H01L21/8239
CPC分类号： H01L27/228 , H01L21/76826 , H01L21/76834 , H01L21/76846 , H01L21/76883
摘要： To provide a technology capable of improving the property of an MRAM in a semiconductor device containing the MRAM.A plasma treatment is performed on the surface of an interlayer insulating film for which a wiring and a digit line are formed. Firstly, a semiconductor substrate is carried in a chamber, and a mixed gas that includes molecules containing nitrogen (ammonia gas) and inert molecules not containing nitrogen (hydrogen gas, helium, argon) is introduced into the chamber. On this occasion, the plasma treatment is performed by introducing the mixed gas under such a condition that the flow rate of the inert molecules not containing nitrogen is larger than that of the molecules containing nitrogen, and the mixed gas is turned into a plasma.
摘要翻译：提供能够提高包含MRAM的半导体器件中MRAM性能的技术。在形成布线和数字线的层间绝缘膜的表面上进行等离子体处理。首先，将半导体基板载置在室内，将包含氮（氨）的分子和不含氮的惰性分子（氢气，氦，氩））的混合气体引入室内。在这种情况下，通过在不含氮的惰性分子的流量比含有氮的分子的流量大的条件下引入混合气体进行等离子体处理，将混合气体变成等离子体。

4. 发明授权

US08089112B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08089112B2
公开(公告)日：2012-01-03
申请号：US13053695
申请日：2011-03-22
申请人： Tatsunori Murata , Mikio Tsujiuchi
发明人： Tatsunori Murata , Mikio Tsujiuchi
IPC分类号： H01L21/02
CPC分类号： H01L27/224 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F41/302 , H01F41/307 , H01L43/08 , H01L43/12
摘要： The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.
摘要翻译：本发明使得可以获得：能够形成高可靠性上线的半导体器件，而对MTJ器件的磁性材料的性能没有有害影响; 及其制造方法。使用可还原NH3或H2作为预处理进行等离子体处理。此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 成膜温度设定在200〜350℃的范围。

5. 发明申请

US20110169113A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110169113A1
公开(公告)日：2011-07-14
申请号：US13053695
申请日：2011-03-22
申请人： Tatsunori Murata , Mikio Tsujiuchi
发明人： Tatsunori Murata , Mikio Tsujiuchi
IPC分类号： H01L29/82
CPC分类号： H01L27/224 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F41/302 , H01F41/307 , H01L43/08 , H01L43/12
摘要： The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.
摘要翻译：本发明使得可以获得：能够形成高可靠性的上线而不会对MTJ装置的磁性材料的性质产生有害影响的半导体器件; 及其制造方法。使用可还原NH3或H2作为预处理进行等离子体处理。此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 成膜温度设定在200〜350℃的范围。

6. 发明授权

US07939871B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07939871B2
公开(公告)日：2011-05-10
申请号：US12832505
申请日：2010-07-08
申请人： Tatsunori Murata , Mikio Tsujiuchi
发明人： Tatsunori Murata , Mikio Tsujiuchi
IPC分类号： H01L21/02
CPC分类号： H01L27/224 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F41/302 , H01F41/307 , H01L43/08 , H01L43/12
摘要： The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.
摘要翻译：本发明使得可以获得：能够形成高可靠性上线的半导体器件，而对MTJ器件的磁性材料的性能没有有害影响; 及其制造方法。使用可还原NH3或H2作为预处理进行等离子体处理。此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 成膜温度设定在200〜350℃的范围。

7. 发明授权

US08216859B2 Manufacturing method of semiconductor device having memory element with protective film 有权
标题翻译：具有保护膜的存储元件的半导体器件的制造方法
公开(公告)号：US08216859B2
公开(公告)日：2012-07-10
申请号：US13069982
申请日：2011-03-23
申请人： Tatsunori Murata , Mikio Tsujiuchi , Ryoji Matsuda
发明人： Tatsunori Murata , Mikio Tsujiuchi , Ryoji Matsuda
IPC分类号： H01L21/00
CPC分类号： H01L27/228 , G11C11/16
摘要： To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH3 but composed of SiH4/N2/helium (He). The film forming temperature is set at from 200 to 350° C. More ideally, a flow rate ratio of He to SiH4 is set at from 100 to 125.
摘要翻译：为了提供能够形成具有良好绝缘性能的氮化硅膜作为MTJ元件的保护膜的半导体器件的制造方法，而不会劣化MTJ元件的性能。本发明的方法包括以下步骤：在使用平板等离子体CVD装置作为成膜装置的同时，在包括MTJ元件部分（MTJ元件和上电极）的整个表面上形成氮化硅膜，以及不含 NH3，但由SiH4 / N2 /氦（He）组成。成膜温度设定在200〜350℃。更理想的是，将He与SiH4的流量比设定为100〜125。

8. 发明申请

US20110221063A1 Manufacturing Method of Semiconductor Device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20110221063A1
公开(公告)日：2011-09-15
申请号：US13046331
申请日：2011-03-11
申请人： Kazuhito Ichinose , Kotaro Kihara , Tatsunori Murata
发明人： Kazuhito Ichinose , Kotaro Kihara , Tatsunori Murata
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76831 , H01L23/481 , H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.
摘要翻译：将钨构件埋入形成在要形成盲孔贯通孔的晶片中的盲孔中的工序。在晶片周围进行成膜（用于形成钨构件），在钨膜下面的阻挡金属的外周的钨构件的外周部位置。该方法使得可以将可能相对较薄的钨构件埋入可能相对较大的盲孔中，以减少晶片的翘曲，并进一步防止钨构件下方的下层被剥离在晶片的周边。

9. 发明申请

US20060091451A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060091451A1
公开(公告)日：2006-05-04
申请号：US11254725
申请日：2005-10-21
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L23/52
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
摘要翻译：为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜，层间绝缘膜。

10. 发明授权

US08492847B2 Semiconductor device having insulating film with increased tensile stress and manufacturing method thereof 有权
标题翻译：具有拉伸应力增加的绝缘膜的半导体装置及其制造方法
公开(公告)号：US08492847B2
公开(公告)日：2013-07-23
申请号：US13341421
申请日：2011-12-30
申请人： Tatsunori Murata , Yuki Koide
发明人： Tatsunori Murata , Yuki Koide
IPC分类号： H01L21/70 , H01L21/4763
CPC分类号： H01L29/7843 , H01L21/2686 , H01L21/28518 , H01L21/76802 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Over a semiconductor substrate, a silicon nitride film is formed so as to cover n-channel MISFETs. The silicon nitride film is a laminate film which may be made of first, second, and third silicon nitride films. The total film thickness of the first and second silicon nitride films is smaller than half a spacing between a first sidewall spacer and a second sidewall spacer. After being deposited, the first and second silicon nitride films are subjected to treatments to have increased tensile stresses. The total film thickness of the first, second, and third silicon nitride films is not less than half the spacing between the first and second sidewall spacers. The third silicon nitride film is not subjected to any tensile-stress-increasing treatment, or may be subjected to a lesser amount of such treatment.
摘要翻译：在半导体衬底上形成氮化硅膜以覆盖n沟道MISFET。氮化硅膜是可由第一，第二和第三氮化硅膜制成的层压膜。第一和第二氮化硅膜的总膜厚度小于第一侧壁间隔物和第二侧壁间隔物之间的间隔的一半。沉积后，对第一和第二氮化硅膜进行处理以增加拉伸应力。第一，第二和第三氮化硅膜的总膜厚度不小于第一和第二侧壁间隔物之间的间距的一半。第三氮化硅膜不经受任何拉伸应力增加处理，或者可以进行较少量的这种处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式