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1. 发明授权

US07924052B1 Field programmable gate array architecture having Clos network-based input interconnect 有权
标题翻译：具有基于Clos网络的输入互连的现场可编程门阵列结构
公开(公告)号：US07924052B1
公开(公告)日：2011-04-12
申请号：US12361835
申请日：2009-01-29
申请人： Wenyi Feng , Jonathan Greene , Sinan Kaptanoglu
发明人： Wenyi Feng , Jonathan Greene , Sinan Kaptanoglu
IPC分类号： H01L25/00
CPC分类号： H03K19/17736
摘要： A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.
摘要翻译：在具有基于群集的架构的可编程逻辑设备中使用的集群内部路由网络采用基于Clos网络的路由架构。路由架构是多级阻塞架构，其中第一级的输入数量超过了第一级的输出数量。

2. 发明授权

US07408383B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
标题翻译：具有两级集群输入互连方案的FPGA架构，无带宽限制
公开(公告)号：US07408383B1
公开(公告)日：2008-08-05
申请号：US11855974
申请日：2007-09-14
申请人： Wenyi Feng , Sinan Kaptanoglu
发明人： Wenyi Feng , Sinan Kaptanoglu
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736
摘要： An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
摘要翻译：用于可编程逻辑器件的互连架构包括多个互连路由线。多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。多个第二级多路复用器被组织成多路复用器组。多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。第二级复用器的数据输入连接到第一级复用器的输出端，使得每个第一级多路复用器的每个输出端连接到每个复用器组中只有一个二级多路复用器的输入。

3. 发明授权

US07924053B1 Clustered field programmable gate array architecture 有权
标题翻译：集群现场可编程门阵列架构
公开(公告)号：US07924053B1
公开(公告)日：2011-04-12
申请号：US12362844
申请日：2009-01-30
申请人： Sinan Kaptanoglu , Wenyi Feng
发明人： Sinan Kaptanoglu , Wenyi Feng
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group. Groups are pitch matched to logic function generators to optimize and modularize area. Provision is made for global and local control of the sequential elements.
摘要翻译：公开了一种用于现场可编程门阵列集成电路器件的逻辑集群。集群包括多个功能块和三个级别的路由多路复用器。外部信号主要进入第三级多路复用器的逻辑集群，其中几个信号进入第二级。组合输出反馈到第一和第二电平复用器，而顺序输出反馈到第三级多路复用器。逻辑函数发生器具有可变输入，具有不同的传播延迟。第一和第二级多路复用器之间的路由信号被分组成速度等级并且根据其速度等级耦合到与不同逻辑函数发生器相关联的第一级复用器。第二和第三级复用器被组织成组，使得第二和第三级多路复用器之间的路由信号可以被定位在该组占用的区域内。组与逻辑功能发生器匹配，优化和模块化区域。规定了全局和本地对顺序元素的控制。

4. 发明授权

US07545169B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
标题翻译：具有两级集群输入互连方案的FPGA架构，无带宽限制
公开(公告)号：US07545169B1
公开(公告)日：2009-06-09
申请号：US12173225
申请日：2008-07-15
申请人： Wenyi Feng , Sinan Kaptanoglu
发明人： Wenyi Feng , Sinan Kaptanoglu
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736
摘要： An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
摘要翻译：用于可编程逻辑器件的互连架构包括多个互连路由线。多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。多个第二级多路复用器被组织成多路复用器组。多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。第二级复用器的数据输入连接到第一级复用器的输出，使得每个第一级多路复用器的每个输出连接到每个多路复用器组中仅一个第二级多路复用器的输入。

5. 发明申请

US20120280711A1 FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES 有权
标题翻译： FPGA RAM块优化用作寄存器文件
公开(公告)号：US20120280711A1
公开(公告)日：2012-11-08
申请号：US13463232
申请日：2012-05-03
申请人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

6. 发明申请

US20100271068A1 LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA 有权
标题翻译：逻辑模块，包括用于FPGA的多个添加器
公开(公告)号：US20100271068A1
公开(公告)日：2010-10-28
申请号：US12823266
申请日：2010-06-25
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： H03K19/21
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

7. 发明授权

US08085064B2 Logic module including versatile adder for FPGA 有权
标题翻译：逻辑模块包括FPGA通用加法器
公开(公告)号：US08085064B2
公开(公告)日：2011-12-27
申请号：US12823266
申请日：2010-06-25
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

8. 发明授权

US07772879B1 Logic module including versatile adder for FPGA 有权
标题翻译：逻辑模块包括FPGA通用加法器
公开(公告)号：US07772879B1
公开(公告)日：2010-08-10
申请号：US12101589
申请日：2008-04-11
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

9. 发明授权

US08446170B2 FPGA RAM blocks optimized for use as register files 有权
标题翻译：优化的FPGA RAM块用作寄存器文件
公开(公告)号：US08446170B2
公开(公告)日：2013-05-21
申请号：US13463232
申请日：2012-05-03
申请人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

10. 发明授权

US08481903B2 Systems, methods, and apparatuses including a moveable optical component for detecting optical signals from a sample 有权
标题翻译：包括用于检测来自样品的光信号的可移动光学部件的系统，方法和装置
公开(公告)号：US08481903B2
公开(公告)日：2013-07-09
申请号：US13041194
申请日：2011-03-04
申请人： Alexander Triener , Erik Allegoren , Wenyi Feng , Dale Buermann , Erik Olson , James Osmus
发明人： Alexander Triener , Erik Allegoren , Wenyi Feng , Dale Buermann , Erik Olson , James Osmus
IPC分类号： G02B7/04
CPC分类号： C12Q1/6874 , C12Q1/6837 , G01N21/6428 , G01N21/645 , G01N21/6456
摘要： An optical system configured to detect optical signals during imaging sessions. The optical system includes an objective lens that has a collecting end that is positioned proximate to a sample and configured to receive optical signals therefrom. The optical system also includes a removable path compensator that is configured to be located at an imaging position between the collecting end of the objective lens and the sample. The path compensator adjusts an optical path of the light emissions when in the imaging position. Also, the optical system includes a transfer device that is configured to move the path compensator. The transfer device locates the path compensator at the imaging position for a first imaging session and removes the path compensator from the imaging position for a second imaging session.
摘要翻译：一种配置成在成像会话期间检测光信号的光学系统。光学系统包括物镜，该物镜具有位于样品附近并被配置为从其接收光信号的收集端。光学系统还包括被配置为位于物镜的收集端和样品之间的成像位置处的可移除路径补偿器。路径补偿器在成像位置调整光发射的光路。此外，光学系统包括被配置为移动路径补偿器的传送装置。传送装置将路径补偿器定位在用于第一成像会话的成像位置处，并从第二成像会话的成像位置移除路径补偿器。

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