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1. 发明申请

US20120280711A1 FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES 有权
标题翻译： FPGA RAM块优化用作寄存器文件
公开(公告)号：US20120280711A1
公开(公告)日：2012-11-08
申请号：US13463232
申请日：2012-05-03
申请人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

2. 发明授权

US08446170B2 FPGA RAM blocks optimized for use as register files 有权
标题翻译：优化的FPGA RAM块用作寄存器文件
公开(公告)号：US08446170B2
公开(公告)日：2013-05-21
申请号：US13463232
申请日：2012-05-03
申请人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

3. 发明授权

US08085064B2 Logic module including versatile adder for FPGA 有权
标题翻译：逻辑模块包括FPGA通用加法器
公开(公告)号：US08085064B2
公开(公告)日：2011-12-27
申请号：US12823266
申请日：2010-06-25
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

4. 发明授权

US07772879B1 Logic module including versatile adder for FPGA 有权
标题翻译：逻辑模块包括FPGA通用加法器
公开(公告)号：US07772879B1
公开(公告)日：2010-08-10
申请号：US12101589
申请日：2008-04-11
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

5. 发明授权

US07924052B1 Field programmable gate array architecture having Clos network-based input interconnect 有权
标题翻译：具有基于Clos网络的输入互连的现场可编程门阵列结构
公开(公告)号：US07924052B1
公开(公告)日：2011-04-12
申请号：US12361835
申请日：2009-01-29
申请人： Wenyi Feng , Jonathan Greene , Sinan Kaptanoglu
发明人： Wenyi Feng , Jonathan Greene , Sinan Kaptanoglu
IPC分类号： H01L25/00
CPC分类号： H03K19/17736
摘要： A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.
摘要翻译：在具有基于群集的架构的可编程逻辑设备中使用的集群内部路由网络采用基于Clos网络的路由架构。路由架构是多级阻塞架构，其中第一级的输入数量超过了第一级的输出数量。

6. 发明申请

US20100271068A1 LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA 有权
标题翻译：逻辑模块，包括用于FPGA的多个添加器
公开(公告)号：US20100271068A1
公开(公告)日：2010-10-28
申请号：US12823266
申请日：2010-06-25
申请人： Wenyi Feng , Jonathan Greene
发明人： Wenyi Feng , Jonathan Greene
IPC分类号： H03K19/21
CPC分类号： H03K19/1737 , G06F7/503 , H03K19/17728
摘要： A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.
摘要翻译：用于FPGA的逻辑模块包括由2：1多路复用器的N级树形成的LUT。 LUT的N个输入中的每一个连接到树的一个级别中的多路复用器的选择输入。在树的叶片处的每个数据输入由产生逻辑0或逻辑1的配置存储器单元驱动。在树的最后一级的单个多路复用器的输出形成Y输出，并耦合到 XOR门的一个输入和双输入进位多路复用器的选择输入。进位多路复用器的0输入耦合到G输入。 CI输入耦合到XOR门的另一个输入端和进位复用器的1个输入端。

7. 发明授权

US08269203B2 Resistive RAM devices for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的电阻式RAM器件
公开(公告)号：US08269203B2
公开(公告)日：2012-09-18
申请号：US12829300
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

8. 发明授权

US07538576B2 Non-volatile look-up table for an FPGA 有权
标题翻译： FPGA的非易失性查找表
公开(公告)号：US07538576B2
公开(公告)日：2009-05-26
申请号：US11858341
申请日：2007-09-20
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。多路复用器具有x地址输入，其中2x = n，如本领域已知的。多路复用器的输出通过上拉晶体管耦合到VCC。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

9. 发明授权

US07301821B1 Volatile data storage in a non-volatile memory cell array 失效
标题翻译：易失性数据存储在非易失性存储单元阵列中
公开(公告)号：US07301821B1
公开(公告)日：2007-11-27
申请号：US11251074
申请日：2005-10-13
申请人： Jonathan Greene , Robert M. Salter, III
发明人： Jonathan Greene , Robert M. Salter, III
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/04 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/3431 , G11C29/50 , H03K19/17776 , H03K19/1778
摘要： A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.
摘要翻译：一种用于将数据存储在非易失性存储单元阵列的存储单元中的节点的方法，包括将非易失性存储单元阵列的非易失性设备设置为期望状态的步骤，将上拉设备和非易失性设备偏置所述非易失性存储单元阵列的第一组行到关闭状态，将数据加载到所述非易失性存储单元阵列的列线上并且偏置所述非易失性存储单元阵列的存储单元中的第二组行中的非易失性设备，非易失性存储单元阵列，用于存储来自非易失性存储单元阵列的存储单元中节点上列列的数据。

10. 发明申请

US20070047330A1 NON-VOLATILE LOOK-UP TABLE FOR AN FPGA 有权
标题翻译： FPGA的非易失性查看表
公开(公告)号：US20070047330A1
公开(公告)日：2007-03-01
申请号：US11551973
申请日：2006-10-23
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： G11C7/10
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。多路复用器的输出通过上拉晶体管耦合到V CC。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

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