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    • 2. 发明授权
      US07408383B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
    • FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation
    • 具有两级集群输入互连方案的FPGA架构，无带宽限制
    • US07408383B1
    • 2008-08-05
    • US11855974
    • 2007-09-14
    • Wenyi Feng , Sinan Kaptanoglu
    • Wenyi Feng , Sinan Kaptanoglu
    • H01L25/00 , H03K19/177
    • H03K19/17736
    • An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
    • 用于可编程逻辑器件的互连架构包括多个互连路由线。 多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。 多个第二级多路复用器被组织成多路复用器组。 多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。 每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。 第二级复用器的数据输入连接到第一级复用器的输出端，使得每个第一级多路复用器的每个输出端连接到每个复用器组中只有一个二级多路复用器的输入。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US07924053B1 Clustered field programmable gate array architecture 有权
    • Clustered field programmable gate array architecture
    • 集群现场可编程门阵列架构
    • US07924053B1
    • 2011-04-12
    • US12362844
    • 2009-01-30
    • Sinan Kaptanoglu , Wenyi Feng
    • Sinan Kaptanoglu , Wenyi Feng
    • H01L25/00
    • H03K19/177
    • A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group. Groups are pitch matched to logic function generators to optimize and modularize area. Provision is made for global and local control of the sequential elements.
    • 公开了一种用于现场可编程门阵列集成电路器件的逻辑集群。 集群包括多个功能块和三个级别的路由多路复用器。 外部信号主要进入第三级多路复用器的逻辑集群，其中几个信号进入第二级。 组合输出反馈到第一和第二电平复用器，而顺序输出反馈到第三级多路复用器。 逻辑函数发生器具有可变输入，具有不同的传播延迟。 第一和第二级多路复用器之间的路由信号被分组成速度等级并且根据其速度等级耦合到与不同逻辑函数发生器相关联的第一级复用器。 第二和第三级复用器被组织成组，使得第二和第三级多路复用器之间的路由信号可以被定位在该组占用的区域内。 组与逻辑功能发生器匹配，优化和模块化区域。 规定了全局和本地对顺序元素的控制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US07545169B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
    • FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation
    • 具有两级集群输入互连方案的FPGA架构，无带宽限制
    • US07545169B1
    • 2009-06-09
    • US12173225
    • 2008-07-15
    • Wenyi Feng , Sinan Kaptanoglu
    • Wenyi Feng , Sinan Kaptanoglu
    • H01L25/00 , H03K19/177
    • H03K19/17736
    • An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
    • 用于可编程逻辑器件的互连架构包括多个互连路由线。 多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。 多个第二级多路复用器被组织成多路复用器组。 多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。 每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。 第二级复用器的数据输入连接到第一级复用器的输出，使得每个第一级多路复用器的每个输出连接到每个多路复用器组中仅一个第二级多路复用器的输入。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07944238B2 (N+1) input flip-flop packing with logic in FPGA architectures 有权
    • (N+1) input flip-flop packing with logic in FPGA architectures
    • （N + 1）输入触发器封装，具有FPGA架构中的逻辑
    • US07944238B2
    • 2011-05-17
    • US12717315
    • 2010-03-04
    • Sinan Kaptanoglu
    • Sinan Kaptanoglu
    • G06F7/38 , H03K19/177
    • H03K19/1737 , H03K19/17728
    • A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
    • 逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。 时钟复用器具有耦合到时钟资源的输入和输出。 输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。 触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。 逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。 触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明申请
      US20050184753A1 Block level routing architecture in a field programmable gate array 失效
    • Block level routing architecture in a field programmable gate array
    • 块级路由架构在现场可编程门阵列中
    • US20050184753A1
    • 2005-08-25
    • US11088621
    • 2005-03-23
    • Sinan Kaptanoglu
    • Sinan Kaptanoglu
    • H01L27/118 , H03K19/177
    • H03K19/17736 , H01L27/11803
    • An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks , in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.
    • FPGA架构具有顶级，中级和低级。 该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。 在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。 中层层次的B16x16瓦片是16块16块阵列。 中间级别的路由资源是包括互连导体组的高速公路路由信道M 1，M 2和M 3。 在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。 每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M 1，M 2和M 3提供每个B1块的接入。 每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。 每组三个互连导体连接到扩展块（EB）3x3开关矩阵的第一侧。 每个EB 3x3开关矩阵的第二面耦合到E-tab。 在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06934927B2 Turn architecture for routing resources in a field programmable gate array 有权
    • Turn architecture for routing resources in a field programmable gate array
    • US06934927B2
    • 2005-08-23
    • US10429003
    • 2003-04-30
    • Sinan Kaptanoglu
    • Sinan Kaptanoglu
    • G06F17/50 , H03K17/693 , H03K19/177 , H01L25/00
    • H03K19/17736 , H03K19/17796
    • An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles. At the intersections of each of the expressway routing channels M1, M2, and M3 in the horizontal direction with the expressway routing channels M1, M2 and M3 in the vertical direction is an expressway turn (E-turn) disposed at the center of each B2×2 tile. An E-turn is a passive device that includes a matrix of reprogrammable switches. The reprogrammable switches are preferably a pass device controlled by an SRAM bit. The interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn may be coupled to many of the other interconnect conductors in the expressway routing channels M1, M2 and M3 that come into the E-turn by the programmable switches. Further, the interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn continue in the same direction through the E-turn, even though the interconnect conductors are coupled to other interconnect conductors by the reprogrammable switches.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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