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1. 发明授权

US08138538B2 Interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US08138538B2
公开(公告)日：2012-03-20
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

2. 发明申请

US20100090264A1 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US20100090264A1
公开(公告)日：2010-04-15
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

3. 发明申请

US20090302380A1 Word Line to Bit Line Spacing Method and Apparatus 有权
标题翻译：字线对位线间距法和装置
公开(公告)号：US20090302380A1
公开(公告)日：2009-12-10
申请号：US12134740
申请日：2008-06-06
申请人： Werner Graf , Lars Heineck , Martin Popp
发明人： Werner Graf , Lars Heineck , Martin Popp
IPC分类号： H01L27/105 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/743 , H01L27/10882 , H01L27/10885 , H01L27/10891
摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.
摘要翻译：在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。

4. 发明授权

US07838928B2 Word line to bit line spacing method and apparatus 有权
标题翻译：字线到位线间距法和装置
公开(公告)号：US07838928B2
公开(公告)日：2010-11-23
申请号：US12134740
申请日：2008-06-06
申请人： Werner Graf , Lars Heineck , Martin Popp
发明人： Werner Graf , Lars Heineck , Martin Popp
IPC分类号： H01L29/792
CPC分类号： H01L21/76232 , H01L21/743 , H01L27/10882 , H01L27/10885 , H01L27/10891
摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.
摘要翻译：在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。

5. 发明授权

US07094674B2 Method for production of contacts on a wafer 有权
公开(公告)号：US07094674B2
公开(公告)日：2006-08-22
申请号：US10739477
申请日：2003-12-18
申请人： Werner Graf , Henning Haffner , Johannes Kowalewski , Lars Heineck
发明人： Werner Graf , Henning Haffner , Johannes Kowalewski , Lars Heineck
IPC分类号： H01L21/44
CPC分类号： H01L27/10888 , H01L21/76897
摘要： The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

6. 发明申请

US20060141756A1 Method for producing a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20060141756A1
公开(公告)日：2006-06-29
申请号：US11282432
申请日：2005-11-18
申请人： Werner Graf , Lars Heineck , Jana Horst
发明人： Werner Graf , Lars Heineck , Jana Horst
IPC分类号： H01L21/331 , H01L21/265
CPC分类号： H01L27/105 , H01L27/1052
摘要： In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.
摘要翻译：在制造半导体结构的方法中，提供了具有顶表面的衬底的半导体。栅极电介质层设置在顶表面上，并且在栅极介电层上提供有具有第一多个栅极堆叠的存储单元阵列区域和具有第二多个栅极堆叠的外围元件区域。在存储单元阵列区域和外围元件区域上提供介电层。执行存储单元阵列区域和外围元件区域上的第一源极/漏极注入，形成存储单元阵列区域上的阻挡掩模，使用阻挡掩模去除电介质层，并且使用第二源极/漏极注入在存储单元阵列区域和外围元件区域上进行，其中存储单元阵列区域被掩模保护。

7. 发明授权

US07018781B2 Method for fabricating a contact hole plane in a memory module 失效
标题翻译：用于在存储器模块中制造接触孔平面的方法
公开(公告)号：US07018781B2
公开(公告)日：2006-03-28
申请号：US10811509
申请日：2004-03-29
申请人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
发明人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
IPC分类号： G03F7/00
CPC分类号： H01L27/10888 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76897 , H01L27/10894
摘要： Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.
摘要翻译：公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

8. 发明申请

US20080315326A1 Method for forming an integrated circuit having an active semiconductor device and integrated circuit 审中-公开
标题翻译：用于形成具有有源半导体器件和集成电路的集成电路的方法
公开(公告)号：US20080315326A1
公开(公告)日：2008-12-25
申请号：US11821274
申请日：2007-06-21
申请人： Werner Graf , Ines Uhlig , Daniel Koehler , Joerg Radecker , Lars Heineck
发明人： Werner Graf , Ines Uhlig , Daniel Koehler , Joerg Radecker , Lars Heineck
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L27/10873 , H01L21/3083 , H01L21/31144 , H01L27/10867 , H01L27/10894
摘要： An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.
摘要翻译：具有有源半导体器件的集成电路形成包括由先前形成的导体线限定的沟槽。

9. 发明申请

US20070290249A1 Integrated Circuit Including a Memory Cell Array 审中-公开
标题翻译：包含存储单元阵列的集成电路
公开(公告)号：US20070290249A1
公开(公告)日：2007-12-20
申请号：US11844853
申请日：2007-08-24
申请人： Martin Popp , Frank Jakubowski , Juergen Holz , Lars Heineck
发明人： Martin Popp , Frank Jakubowski , Juergen Holz , Lars Heineck
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L21/26586 , H01L27/0207 , H01L27/10823 , H01L27/10829 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.
摘要翻译：集成电路包括具有晶体管的存储单元的存储单元阵列。晶体管形成在有源区域中。存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。有源区域沿第二方向延伸。晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。此外，字线设置在位线之上。

10. 发明授权

US06916721B2 Method for fabricating a trench capacitor with an insulation collar 失效
标题翻译：用于制造具有绝缘套圈的沟槽电容器的方法
公开(公告)号：US06916721B2
公开(公告)日：2005-07-12
申请号：US10722360
申请日：2003-11-26
申请人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
发明人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
IPC分类号： H01L21/20 , H01L21/334 , H01L21/425 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.
摘要翻译：一种在衬底中制造具有绝缘套环的沟槽电容器的方法，其使用具有相应掩模开口的硬掩模经由掩埋触点将其一侧的衬底电连接。

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