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1. 发明申请

US20120300545A1 SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH 有权
标题翻译：用于在NAND闪存中生成软信息的系统和方法
公开(公告)号：US20120300545A1
公开(公告)日：2012-11-29
申请号：US13477678
申请日：2012-05-22
申请人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
发明人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3427
摘要： Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
摘要翻译：提供系统和方法以产生与存储器单元的阈值电压相关的软信息。用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。测量响应于所施加的参考信号的存储单元的输出。所施加的参考信号包括电压值和位置信息。基于参考信号的位置信息来识别单个箱。基于存储单元的输出和参考信号的电压值，将识别的箱分成多于一个箱。新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

2. 发明授权

US09065623B1 Mixed mapping for rate compatible trellis coded modulation 有权
标题翻译：用于速率兼容网格编码调制的混合映射
公开(公告)号：US09065623B1
公开(公告)日：2015-06-23
申请号：US13249754
申请日：2011-09-30
申请人： Zhengang Chen , Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Zhengang Chen , Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： H04L1/00 , H03M13/25 , H04L27/18 , H04L27/34
CPC分类号： H04L1/006 , H03M13/25 , H03M13/256 , H03M13/6362 , H04L1/0041 , H04L1/0069 , H04L27/186 , H04L27/3416
摘要： Systems, methods, apparatus, and techniques are provided for producing encoded trellis coded modulation (TCM) data from user information. Encoding parameters are selected based on a target information rate. The encoding parameters include a first dimensionality value and a second dimensionality value. A first part of the user information is encoded based on the first dimensionality value to produce a first number of coded bits, and a second part of the user information is encoded based on the second dimensionality value to produce a second number of coded bits.
摘要翻译：提供了系统，方法，装置和技术，用于从用户信息产生编码网格编码调制（TCM）数据。基于目标信息速率来选择编码参数。编码参数包括第一维度值和第二维度值。用户信息的第一部分基于第一维度值进行编码，以产生第一数量的编码比特，并且基于第二维度值对用户信息的第二部分进行编码以产生第二数量的编码比特。

3. 发明授权

US08681564B2 Systems and methods for generating soft information in NAND flash 有权
标题翻译：用于在NAND闪存中生成软信息的系统和方法
公开(公告)号：US08681564B2
公开(公告)日：2014-03-25
申请号：US13477678
申请日：2012-05-22
申请人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
发明人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C16/00
CPC分类号： G11C16/06 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3427
摘要： Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
摘要翻译：提供系统和方法以产生与存储器单元的阈值电压相关的软信息。用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。测量响应于所施加的参考信号的存储单元的输出。所施加的参考信号包括电压值和位置信息。基于参考信号的位置信息来识别单个箱。基于存储单元的输出和参考信号的电压值，将识别的箱分成多于一个箱。新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

4. 发明申请

US20120317460A1 IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS 有权
标题翻译：存储系统中硬错误的识别和缓解
公开(公告)号：US20120317460A1
公开(公告)日：2012-12-13
申请号：US13481376
申请日：2012-05-25
申请人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
发明人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
IPC分类号： H03M13/05 , G06F11/10 , G11C16/04
CPC分类号： G06F11/1072 , G06F11/1048 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/45
摘要： Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.
摘要翻译：实施例提供了一种方法，包括：估计存储器的多个存储器单元的第一组对数似然比（LLR）值; 基于第一组LLR值，执行第一纠错码（ECC）解码操作; 响应于确定所述第一ECC解码操作的故障，通过调整所述第一组LLR值，生成所述多个存储器单元的第二组LLR值; 并且基于第二组LLR值，执行第二ECC解码操作。

5. 发明授权

US08825945B2 Mapping different portions of data to different pages of multi-level non-volatile memory 有权
标题翻译：将不同部分的数据映射到多级非易失性存储器的不同页面
公开(公告)号：US08825945B2
公开(公告)日：2014-09-02
申请号：US13360626
申请日：2012-01-27
申请人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括具有多个多级存储单元的非易失性存储器结构，处理设备和控制器。控制器被配置为将数据段的第一组连续位的第一部分映射到与多个多级存储器单元相关联的第一页，并且映射数据的第一组连续位的第二部分分段到与多个多级存储器单元相关联的第二页。第一页与第一重要性的位相关联，并且第二页与第二重要性的位相关联。

6. 发明申请

US20120198135A1 Mapping Data to Non-Volatile Memory 有权
标题翻译：将数据映射到非易失性存储器
公开(公告)号：US20120198135A1
公开(公告)日：2012-08-02
申请号：US13360626
申请日：2012-01-27
申请人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： G06F12/02 , G06F12/06 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括具有多个多级存储单元的非易失性存储器结构，处理设备和控制器。控制器被配置为将数据段的第一组连续位的第一部分映射到与多个多级存储器单元相关联的第一页，并且映射数据的第一组连续位的第二部分分段到与多个多级存储器单元相关联的第二页。第一页与第一重要性的位相关联，并且第二页与第二重要性的位相关联。

7. 发明授权

US09009574B2 Identification and mitigation of hard errors in memory systems 有权
标题翻译：识别和缓解内存系统中的硬错误
公开(公告)号：US09009574B2
公开(公告)日：2015-04-14
申请号：US13481376
申请日：2012-05-25
申请人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
发明人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
IPC分类号： H03M13/00 , G11C29/02 , G06F11/10 , G11C29/52 , G11C29/04
CPC分类号： G06F11/1072 , G06F11/1048 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/45
摘要： Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.
摘要翻译：实施例提供了一种方法，包括：估计存储器的多个存储器单元的第一组对数似然比（LLR）值; 基于第一组LLR值，执行第一纠错码（ECC）解码操作; 响应于确定所述第一ECC解码操作的故障，通过调整所述第一组LLR值，生成所述多个存储器单元的第二组LLR值; 并且基于第二组LLR值，执行第二ECC解码操作。

8. 发明授权

US08694868B1 Systems and methods for performing multi-state bit flipping in an LDPC decoder 有权
标题翻译：用于在LDPC解码器中执行多状态位翻转的系统和方法
公开(公告)号：US08694868B1
公开(公告)日：2014-04-08
申请号：US13300323
申请日：2011-11-18
申请人： Shashi Kiran Chilappagari , Nedeljko Varnica , Xueshi Yang , Gregory Burd
发明人： Shashi Kiran Chilappagari , Nedeljko Varnica , Xueshi Yang , Gregory Burd
IPC分类号： H03M13/00
CPC分类号： H03M13/1108 , H03M13/1137 , H03M13/6577
摘要： Systems and methods are provided for decoding data using hard decisions and soft information. In particular, the systems and methods described herein are directed to decoders having variable nodes and check nodes, each with multiple states. The systems and methods include receiving, at a decoder during a first iteration, values for each of a plurality of variable nodes, and determining, during a second iteration, one or more indications for each of a plurality of check nodes based on the one or more values of the variable nodes received during the first iteration. The methods further include updating, at the decoder during the second iteration, the values for each of the variable nodes based on the values of the respective variable node received during the first iteration, and the indications for each of the plurality connected check nodes during the first iteration.
摘要翻译：提供了使用硬判决和软信息对数据进行解码的系统和方法。特别地，这里描述的系统和方法涉及具有可变节点和校验节点的解码器，每个具有多个状态。所述系统和方法包括在第一次迭代期间在解码器处接收多个变量节点中的每一个的值，以及在第二迭代期间，基于所述一个或多个节点在多个检查节点中的每一个确定一个或多个指示在第一次迭代期间接收到的变量节点的更多值。所述方法还包括在第二次迭代期间在解码器处更新基于在第一次迭代期间接收到的相应可变节点的值的每个变量节点的值，以及在该第一迭代期间针对多个连接的校验节点中的每一个的指示第一次迭代

9. 发明授权

US08667361B1 Systems and methods for performing bit flipping in an LDPC decoder 有权
标题翻译：用于在LDPC解码器中执行比特翻转的系统和方法
公开(公告)号：US08667361B1
公开(公告)日：2014-03-04
申请号：US13276525
申请日：2011-10-19
申请人： Nedeljko Varnica , Shashi Kiran Chilappagari , Gregory Burd
发明人： Nedeljko Varnica , Shashi Kiran Chilappagari , Gregory Burd
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , H03M13/1108 , H03M13/373
摘要： Systems and methods are provided for decoding data using hard decisions and erasures. Circuitry receives data from each of a plurality of variable nodes which correspond to bits of data being decoded. Each variable node stores one of at least three values. The circuitry determines processes the values received from the plurality of variable nodes according to a set of processing rules. The processing rules are used to determine a condition related to the values stored by the plurality of variable nodes. The circuitry stores an indication of the stored condition at a check node.
摘要翻译：提供了系统和方法，用于使用硬判决和擦除来对数据进行解码。电路从多个可变节点中的每一个接收数据，这些变量节点对应于被解码的数据位。每个变量节点存储至少三个值中的一个。电路根据一组处理规则确定从多个可变节点接收的值的处理。处理规则用于确定与由多个可变节点存储的值相关的条件。该电路将存储条件的指示存储在校验节点处。

10. 发明授权

US09048879B1 Error correction system using an iterative product code 有权
标题翻译：纠错系统使用迭代产品代码
公开(公告)号：US09048879B1
公开(公告)日：2015-06-02
申请号：US13586710
申请日：2012-08-15
申请人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
发明人： Shaohua Yang , Zining Wu , Gregory Burd , Xueshi Yang , Hongwei Song , Nedeljko Varnica
IPC分类号： H03M13/29 , H04L1/00
CPC分类号： H03M13/2945 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/23 , H03M13/2909 , H03M13/2957 , H03M13/3746 , H04L1/0065
摘要： An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.
摘要翻译：纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。在一些实施例中，在传输侧，在输入节点处接收的输入信号基于交织的代码进行编码，该代码编码输入数据的交错版本以产生第一组码字。第一组码字的至少一部分优选地被划分为多个符号，这些符号基于嵌入的奇偶校验码被编码以提供编码数据。类似地，在一些实施例中，在接收侧，检测所接收的数据以产生检测到的信息和软输出。检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

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