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1. 发明授权

US08458556B2 Low complexity finite precision decoders and apparatus for LDPC codes 有权
标题翻译：低复杂度有限精度解码器和LDPC码装置
公开(公告)号：US08458556B2
公开(公告)日：2013-06-04
申请号：US12900584
申请日：2010-10-08
申请人： Shiva K. Planjery , Shashi Kiran Chilappagari , Bane Vasic , David Declercq
发明人： Shiva K. Planjery , Shashi Kiran Chilappagari , Bane Vasic , David Declercq
IPC分类号： H03M13/00
CPC分类号： H03M13/1171 , H03M13/1117 , H03M13/1137 , H03M13/114 , H03M13/1142 , H03M13/3707 , H03M13/6577 , H04L1/005 , H04L1/0057
摘要： In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented.
摘要翻译：在本发明中，提出了一种新型的用于低密度奇偶校验（LDPC）码的有限精度多级解码器。与标准置信传播（BP）解码器相比，这些解码器的复杂度要低得多。由这些解码器使用的消息基于允许在硬件中表示的比特数被量化到某个等级。特定定义为本发明一部分的消息更新功能用于确定可变节点处的传出消息，并且在校验节点处使用简单最小操作以及模2符号和。提供了一种通用的方法来获得多级解码器，该解码器基于减少陷阱集合造成的故障并提高代码的有保障的纠错能力。因此，这些解码器改进了有限长度图上的迭代解码过程，并且具有在误差区域中优于标准浮点BP解码器的潜力。还提出了用于列重三个LDPC码的3位解码器的描述和装置。

2. 发明授权

US08825945B2 Mapping different portions of data to different pages of multi-level non-volatile memory 有权
标题翻译：将不同部分的数据映射到多级非易失性存储器的不同页面
公开(公告)号：US08825945B2
公开(公告)日：2014-09-02
申请号：US13360626
申请日：2012-01-27
申请人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括具有多个多级存储单元的非易失性存储器结构，处理设备和控制器。控制器被配置为将数据段的第一组连续位的第一部分映射到与多个多级存储器单元相关联的第一页，并且映射数据的第一组连续位的第二部分分段到与多个多级存储器单元相关联的第二页。第一页与第一重要性的位相关联，并且第二页与第二重要性的位相关联。

3. 发明申请

US20120300545A1 SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH 有权
标题翻译：用于在NAND闪存中生成软信息的系统和方法
公开(公告)号：US20120300545A1
公开(公告)日：2012-11-29
申请号：US13477678
申请日：2012-05-22
申请人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
发明人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3427
摘要： Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
摘要翻译：提供系统和方法以产生与存储器单元的阈值电压相关的软信息。用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。测量响应于所施加的参考信号的存储单元的输出。所施加的参考信号包括电压值和位置信息。基于参考信号的位置信息来识别单个箱。基于存储单元的输出和参考信号的电压值，将识别的箱分成多于一个箱。新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

4. 发明申请

US20120198135A1 Mapping Data to Non-Volatile Memory 有权
标题翻译：将数据映射到非易失性存储器
公开(公告)号：US20120198135A1
公开(公告)日：2012-08-02
申请号：US13360626
申请日：2012-01-27
申请人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： G06F12/02 , G06F12/06 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括具有多个多级存储单元的非易失性存储器结构，处理设备和控制器。控制器被配置为将数据段的第一组连续位的第一部分映射到与多个多级存储器单元相关联的第一页，并且映射数据的第一组连续位的第二部分分段到与多个多级存储器单元相关联的第二页。第一页与第一重要性的位相关联，并且第二页与第二重要性的位相关联。

5. 发明授权

US08681564B2 Systems and methods for generating soft information in NAND flash 有权
标题翻译：用于在NAND闪存中生成软信息的系统和方法
公开(公告)号：US08681564B2
公开(公告)日：2014-03-25
申请号：US13477678
申请日：2012-05-22
申请人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
发明人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C16/00
CPC分类号： G11C16/06 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3427
摘要： Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
摘要翻译：提供系统和方法以产生与存储器单元的阈值电压相关的软信息。用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。测量响应于所施加的参考信号的存储单元的输出。所施加的参考信号包括电压值和位置信息。基于参考信号的位置信息来识别单个箱。基于存储单元的输出和参考信号的电压值，将识别的箱分成多于一个箱。新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

6. 发明授权

US08667361B1 Systems and methods for performing bit flipping in an LDPC decoder 有权
标题翻译：用于在LDPC解码器中执行比特翻转的系统和方法
公开(公告)号：US08667361B1
公开(公告)日：2014-03-04
申请号：US13276525
申请日：2011-10-19
申请人： Nedeljko Varnica , Shashi Kiran Chilappagari , Gregory Burd
发明人： Nedeljko Varnica , Shashi Kiran Chilappagari , Gregory Burd
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , H03M13/1108 , H03M13/373
摘要： Systems and methods are provided for decoding data using hard decisions and erasures. Circuitry receives data from each of a plurality of variable nodes which correspond to bits of data being decoded. Each variable node stores one of at least three values. The circuitry determines processes the values received from the plurality of variable nodes according to a set of processing rules. The processing rules are used to determine a condition related to the values stored by the plurality of variable nodes. The circuitry stores an indication of the stored condition at a check node.
摘要翻译：提供了系统和方法，用于使用硬判决和擦除来对数据进行解码。电路从多个可变节点中的每一个接收数据，这些变量节点对应于被解码的数据位。每个变量节点存储至少三个值中的一个。电路根据一组处理规则确定从多个可变节点接收的值的处理。处理规则用于确定与由多个可变节点存储的值相关的条件。该电路将存储条件的指示存储在校验节点处。

7. 发明授权

US08531888B2 Determining optimal reference voltages for progressive reads in flash memory systems 有权
标题翻译：确定闪存系统中逐行读取的最佳参考电压
公开(公告)号：US08531888B2
公开(公告)日：2013-09-10
申请号：US13167896
申请日：2011-06-24
申请人： Shashi Kiran Chilappagari , Xueshi Yang
发明人： Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C11/5642
摘要： A system including a reference voltage module to select a first reference voltage between a first threshold voltage corresponding to a first state of a memory cell and a second threshold voltage corresponding to a second state of the memory cell, a second reference voltage less than the first reference voltage, and a third reference voltage greater than the first reference voltage. The system includes a read module to perform a first read operation to determine a state of the memory cell based on the first reference voltage, and in response to a first failure to decode data read from the memory cell in the first read operation, perform a second read operation to determine the state based on the second reference voltage and a third read operation to determine the state based on the third reference voltage.
摘要翻译：一种包括参考电压模块的系统，用于在对应于存储单元的第一状态的第一阈值电压与对应于存储单元的第二状态的第二阈值电压之间选择第一参考电压，小于第一参考电压的第一参考电压参考电压和大于第一参考电压的第三参考电压。该系统包括读取模块，用于执行第一读取操作以基于第一参考电压确定存储器单元的状态，并且响应于在第一读取操作中对从存储器单元读取的数据进行解码的第一个故障，执行一个第二读取操作，以基于第二参考电压确定状态，以及第三读取操作，以基于第三参考电压来确定状态。

8. 发明授权

US09065623B1 Mixed mapping for rate compatible trellis coded modulation 有权
标题翻译：用于速率兼容网格编码调制的混合映射
公开(公告)号：US09065623B1
公开(公告)日：2015-06-23
申请号：US13249754
申请日：2011-09-30
申请人： Zhengang Chen , Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Zhengang Chen , Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： H04L1/00 , H03M13/25 , H04L27/18 , H04L27/34
CPC分类号： H04L1/006 , H03M13/25 , H03M13/256 , H03M13/6362 , H04L1/0041 , H04L1/0069 , H04L27/186 , H04L27/3416
摘要： Systems, methods, apparatus, and techniques are provided for producing encoded trellis coded modulation (TCM) data from user information. Encoding parameters are selected based on a target information rate. The encoding parameters include a first dimensionality value and a second dimensionality value. A first part of the user information is encoded based on the first dimensionality value to produce a first number of coded bits, and a second part of the user information is encoded based on the second dimensionality value to produce a second number of coded bits.
摘要翻译：提供了系统，方法，装置和技术，用于从用户信息产生编码网格编码调制（TCM）数据。基于目标信息速率来选择编码参数。编码参数包括第一维度值和第二维度值。用户信息的第一部分基于第一维度值进行编码，以产生第一数量的编码比特，并且基于第二维度值对用户信息的第二部分进行编码以产生第二数量的编码比特。

9. 发明授权

US08576625B1 Decoder parameter estimation using multiple memory reads 失效
公开(公告)号：US08576625B1
公开(公告)日：2013-11-05
申请号：US13089135
申请日：2011-04-18
申请人： Xueshi Yang , Shashi Kiran Chilappagari
发明人： Xueshi Yang , Shashi Kiran Chilappagari
IPC分类号： G11C16/06
CPC分类号： G11C16/3422 , G06F11/1068 , G11C16/26
摘要： An apparatus including a memory array and control circuitry. The control circuitry is configured to, based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges. The control circuitry is further configured to, based at least on the number of memory cells that have threshold voltages in each of the plurality of voltage ranges, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage. The control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on the estimated offset amount.

10. 发明申请

US20120317460A1 IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS 有权
标题翻译：存储系统中硬错误的识别和缓解
公开(公告)号：US20120317460A1
公开(公告)日：2012-12-13
申请号：US13481376
申请日：2012-05-25
申请人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
发明人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
IPC分类号： H03M13/05 , G06F11/10 , G11C16/04
CPC分类号： G06F11/1072 , G06F11/1048 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/45
摘要： Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.
摘要翻译：实施例提供了一种方法，包括：估计存储器的多个存储器单元的第一组对数似然比（LLR）值; 基于第一组LLR值，执行第一纠错码（ECC）解码操作; 响应于确定所述第一ECC解码操作的故障，通过调整所述第一组LLR值，生成所述多个存储器单元的第二组LLR值; 并且基于第二组LLR值，执行第二ECC解码操作。

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