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1. 发明授权

US08856431B2 Mixed granularity higher-level redundancy for non-volatile memory 有权
标题翻译：非易失性存储器的混合粒度更高级冗余
公开(公告)号：US08856431B2
公开(公告)日：2014-10-07
申请号：US13565752
申请日：2012-08-02
申请人： Zhengang Chen , Yunxiang Wu
发明人： Zhengang Chen , Yunxiang Wu
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/108 , G11C29/52
摘要： Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.
摘要翻译： NVM的混合级别更高级别的冗余提供了更高级别的冗余操作，具有更好的错误恢复和/或减少的冗余信息开销。例如，以相对更多的冗余信息为代价，具有较不可靠性的诸如相对更易于出现错误的NVM的页面在具有相对更多的错误保护的较高级冗余模式中操作。同时，更具可靠性的NVM块以牺牲相对较少的冗余信息为代价的具有相对较少的错误保护的较高级冗余模式运行。与在较高级冗余模式下操作整个NVM的技术相比，具有相对更少的错误保护的技术相比，本文所述的技术提供更好的错误恢复。与在具有相对更多的错误保护的较高级别冗余模式中操作NVM的整体的技术相比，本文所描述的技术提供减少的冗余信息开销。

2. 发明授权

US09239754B2 Single read based soft-decision decoding of non-volatile memory 有权
标题翻译：单向读取非易失性存储器的软判决解码
公开(公告)号：US09239754B2
公开(公告)日：2016-01-19
申请号：US13567024
申请日：2012-08-04
申请人： Yunxiang Wu , Zhengang Chen , Ning Chen
发明人： Yunxiang Wu , Zhengang Chen , Ning Chen
IPC分类号： G06F11/10 , G11C16/26
CPC分类号： G06F11/1048 , G11C16/26
摘要： A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs.
摘要翻译：固态盘（SSD）控制器通过单次读取执行软判决解码，从而提高诸如SSD的存储子系统的性能，功率和/或可靠性。在第一方面，控制器从硬解码读取的信道参数生成软判决度量，而不需要额外的读取和/或数组访问。在第二方面，控制器使用所生成的软判决度量来执行软解码。在第三方面，当发生硬解码读取错误时，控制器产生软判决度量并且利用产生的软判决度量进行软解码。

3. 发明申请

US20140026003A1 FLASH MEMORY READ ERROR RATE REDUCTION 审中-公开
标题翻译：闪存读取错误速率减少
公开(公告)号：US20140026003A1
公开(公告)日：2014-01-23
申请号：US13555444
申请日：2012-07-23
申请人： Zhengang Chen , Yunxiang Wu
发明人： Zhengang Chen , Yunxiang Wu
IPC分类号： G06F11/07
CPC分类号： G06F11/1048 , G11C16/00 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages.
摘要翻译：公开了一种具有第一电路和第二电路的装置。第一电路可以被配置为（i）在一组数据的第一次读取中产生由存储器电路使用的参考电压，以及（ii）基于多个参数来调整参考电压以降低第二个中的错误率从存储器电路读取该组。第二电路可以被配置为响应于在从存储器电路的第一次读取之后施加到该组的错误校正来更新参数。存储器电路通常被配置为通过调整多个阈值电压将数据存储在非易失性状态。

4. 发明授权

US09009574B2 Identification and mitigation of hard errors in memory systems 有权
标题翻译：识别和缓解内存系统中的硬错误
公开(公告)号：US09009574B2
公开(公告)日：2015-04-14
申请号：US13481376
申请日：2012-05-25
申请人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
发明人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
IPC分类号： H03M13/00 , G11C29/02 , G06F11/10 , G11C29/52 , G11C29/04
CPC分类号： G06F11/1072 , G06F11/1048 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/45
摘要： Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.
摘要翻译：实施例提供了一种方法，包括：估计存储器的多个存储器单元的第一组对数似然比（LLR）值; 基于第一组LLR值，执行第一纠错码（ECC）解码操作; 响应于确定所述第一ECC解码操作的故障，通过调整所述第一组LLR值，生成所述多个存储器单元的第二组LLR值; 并且基于第二组LLR值，执行第二ECC解码操作。

5. 发明授权

US08627183B1 Systems and methods for storing variable rate product codes 有权
标题翻译：用于存储可变费率产品代码的系统和方法
公开(公告)号：US08627183B1
公开(公告)日：2014-01-07
申请号：US13100644
申请日：2011-05-04
申请人： Zhengang Chen , Xueshi Yang
发明人： Zhengang Chen , Xueshi Yang
IPC分类号： H03M13/00
CPC分类号： H03M13/2909 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23
摘要： Systems and methods for storing variable rate product codes are provided. A plurality of row code parity symbols is stored on a storage unit. Each symbol of the row code parity symbols is associated with a different one of a plurality of equal sized portions of information. A plurality of column code parity symbols is computed. Each of the plurality of column code parity symbols is computed based on (1) a respective one of the plurality of row code parity symbols and (2) the portion of information associated with the respective one of the plurality of row code parity symbols. Each of the plurality of column code parity symbols corresponds to one of at least two code rates. The plurality of column code parity symbols is stored on the storage unit.
摘要翻译：提供了用于存储可变速率产品代码的系统和方法。多个行码奇偶校验符号被存储在存储单元上。行码奇偶校验符号的每个符号与多个相等大小的信息部分中的不同的一个相关联。计算多个列码奇偶校验符号。基于（1）多个行码奇偶校验符号中的相应一个和（2）与多个行码奇偶校验符号中的相应一个相关联的信息的部分来计算多个列码奇偶校验符号中的每一个。多个列码奇偶校验符号中的每一个对应于至少两个码率中的一个。多个列码奇偶校验符号被存储在存储单元上。

6. 发明授权

US09065623B1 Mixed mapping for rate compatible trellis coded modulation 有权
标题翻译：用于速率兼容网格编码调制的混合映射
公开(公告)号：US09065623B1
公开(公告)日：2015-06-23
申请号：US13249754
申请日：2011-09-30
申请人： Zhengang Chen , Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
发明人： Zhengang Chen , Shashi Kiran Chilappagari , Xueshi Yang , Gregory Burd
IPC分类号： H04L1/00 , H03M13/25 , H04L27/18 , H04L27/34
CPC分类号： H04L1/006 , H03M13/25 , H03M13/256 , H03M13/6362 , H04L1/0041 , H04L1/0069 , H04L27/186 , H04L27/3416
摘要： Systems, methods, apparatus, and techniques are provided for producing encoded trellis coded modulation (TCM) data from user information. Encoding parameters are selected based on a target information rate. The encoding parameters include a first dimensionality value and a second dimensionality value. A first part of the user information is encoded based on the first dimensionality value to produce a first number of coded bits, and a second part of the user information is encoded based on the second dimensionality value to produce a second number of coded bits.
摘要翻译：提供了系统，方法，装置和技术，用于从用户信息产生编码网格编码调制（TCM）数据。基于目标信息速率来选择编码参数。编码参数包括第一维度值和第二维度值。用户信息的第一部分基于第一维度值进行编码，以产生第一数量的编码比特，并且基于第二维度值对用户信息的第二部分进行编码以产生第二数量的编码比特。

7. 发明授权

US08914696B2 Flash memory read scrub and channel tracking 有权
标题翻译：闪存读取擦除和通道跟踪
公开(公告)号：US08914696B2
公开(公告)日：2014-12-16
申请号：US13597489
申请日：2012-08-29
申请人： Zhengang Chen , Earl T. Cohen
发明人： Zhengang Chen , Earl T. Cohen
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/106
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters.
摘要翻译：公开了一种具有第一电路和第二电路的装置。第一电路可以被配置为（i）在区域的读取擦除期间从存储器电路的区域读取数据，以及（ii）基于（a）数据生成多个统计信息，以及（b）一个或多个位在数据的错误校正期间执行翻转。存储器电路通常被配置为将数据存储在非易失性状态中。可以使用一个或多个参考电压来读取数据。第二电路可以被配置为（i）基于统计信息来更新区域的多个参数，以及（ii）基于参数计算参考电压的更新值。

8. 发明申请

US20120317460A1 IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS 有权
标题翻译：存储系统中硬错误的识别和缓解
公开(公告)号：US20120317460A1
公开(公告)日：2012-12-13
申请号：US13481376
申请日：2012-05-25
申请人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
发明人： Shashi Kiran Chilappagari , Gregory Burd , Zhengang Chen
IPC分类号： H03M13/05 , G06F11/10 , G11C16/04
CPC分类号： G06F11/1072 , G06F11/1048 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/45
摘要： Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.
摘要翻译：实施例提供了一种方法，包括：估计存储器的多个存储器单元的第一组对数似然比（LLR）值; 基于第一组LLR值，执行第一纠错码（ECC）解码操作; 响应于确定所述第一ECC解码操作的故障，通过调整所述第一组LLR值，生成所述多个存储器单元的第二组LLR值; 并且基于第二组LLR值，执行第二ECC解码操作。

9. 发明授权

US08681564B2 Systems and methods for generating soft information in NAND flash 有权
标题翻译：用于在NAND闪存中生成软信息的系统和方法
公开(公告)号：US08681564B2
公开(公告)日：2014-03-25
申请号：US13477678
申请日：2012-05-22
申请人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
发明人： Zhengang Chen , Gregory Burd , Shashi Kiran Chilappagari , Xueshi Yang
IPC分类号： G11C16/00
CPC分类号： G11C16/06 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3427
摘要： Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.
摘要翻译：提供系统和方法以产生与存储器单元的阈值电压相关的软信息。用于存储器单元的阈值电压的范围被划分为这里称为仓的阈值电压值的子区域。测量响应于所施加的参考信号的存储单元的输出。所施加的参考信号包括电压值和位置信息。基于参考信号的位置信息来识别单个箱。基于存储单元的输出和参考信号的电压值，将识别的箱分成多于一个箱。新拆分的箱体以及未分割的所有其他箱体被分配新的箱子索引。

10. 发明申请

US20140068365A1 FLASH MEMORY READ SCRUB AND CHANNEL TRACKING 有权
标题翻译：闪存存储器读取SCRUB和通道跟踪
公开(公告)号：US20140068365A1
公开(公告)日：2014-03-06
申请号：US13597489
申请日：2012-08-29
申请人： Zhengang Chen , Earl T. Cohen
发明人： Zhengang Chen , Earl T. Cohen
IPC分类号： G06F11/07
CPC分类号： G06F11/106
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters.
摘要翻译：公开了一种具有第一电路和第二电路的装置。第一电路可以被配置为（i）在区域的读取擦除期间从存储器电路的区域读取数据，以及（ii）基于（a）数据生成多个统计信息，以及（b）一个或多个位在数据的错误校正期间执行翻转。存储器电路通常被配置为将数据存储在非易失性状态中。可以使用一个或多个参考电压来读取数据。第二电路可以被配置为（i）基于统计信息来更新区域的多个参数，以及（ii）基于参数计算参考电压的更新值。

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