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1. 发明授权

US09647788B2 Low latency multiplexing for optical transport networks 有权
公开(公告)号：US09647788B2
公开(公告)日：2017-05-09
申请号：US13764888
申请日：2013-02-12
申请人： Timothy P. Walker
发明人： Timothy P. Walker
IPC分类号： G01R31/08 , H04L5/14 , H04B7/00 , H04J14/00
CPC分类号： H04J14/00
摘要： Techniques for multiplexing and demultiplexing signals for optical transport networks are presented. A network component comprises a multiplexer component that multiplexes a plurality of signals having a first signal format to produce a multiplexed signal in accordance with a second signal format, while maintaining error correction code (ECC) of such signals and without decoding such signals and associated ECC. The multiplexer component interleaves the plurality of signals with stuffing and adds overhead without generating new ECC. A second network component receives the multiplexed signal as part of a frame in accordance with the second signal format. A demultiplexer component of the second network component demultiplexes the multiplexed signal using the original ECC associated with the plurality of signals, wherein the second network element removes and filters the stuffing from the multiplexed signal and produces a plurality of demultiplexed signals as an output, in accordance with the first signal format.

2. 发明授权

US09588923B2 Flow pinning in a server on a chip 有权
标题翻译：在芯片上的服务器中流动锁定
公开(公告)号：US09588923B2
公开(公告)日：2017-03-07
申请号：US14162903
申请日：2014-01-24
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Keyur Chudgar , Kumar Sankaran
IPC分类号： G06F13/24 , G06F13/38
CPC分类号： G06F13/385
摘要： Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.
摘要翻译：各种实施例提供了芯片上的系统或执行流锁定的芯片上的系统，其中分组或分组流入队列到特定队列，其中每个队列与多处理器/多核系统中的相应核相关联或服务器在芯片上。对于分配给特定处理器的每个数据包流或流，芯片上的服务器可以并行地从同一个以太网接口的多个流处理和进入来自多个队列的数据包。每个队列可以向其分配的处理器发出中断，从而允许每个处理器同时从其各自的队列接收数据包。因此，通过为不同流并行接收和处理数据包，从而增加分组处理速度。

3. 发明授权

US09558123B2 Retrieval hash index 有权
标题翻译：检索散列索引
公开(公告)号：US09558123B2
公开(公告)日：2017-01-31
申请号：US15157597
申请日：2016-05-18
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Kjeld Svendsen
IPC分类号： G06F12/0895 , G06F12/08
CPC分类号： G06F12/0864 , G06F12/0802 , G06F12/0893 , G06F12/0895 , Y02D10/13
摘要： Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.
摘要翻译：提供了便于在电子设备中检索散列索引的系统和方法。该系统包含一个寻址组件，它根据排他或身份生成散列索引。寻址组件可以根据标签值检索散列索引。因此，可以减少所需的存储区域，并且电子设备可以更有效率。

4. 发明授权

US09485039B1 Calibration and tracking of receiver 有权
标题翻译：接收机的校准和跟踪
公开(公告)号：US09485039B1
公开(公告)日：2016-11-01
申请号：US14736874
申请日：2015-06-11
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Moshe Malkin , Tarun Gupta
IPC分类号： H03M1/10 , H04B17/21
CPC分类号： H04B17/21 , H04B17/14
摘要： Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.
摘要翻译：提出了校准交错模数转换器（ADC）阵列的技术。收发器包括包括交错子ADC阵列的ADC组件，以及与辅助子ADC相关联的辅助路径，用于通过将辅助路径信号与阵列中的子ADC的信号进行比较来便于校准采样阵列。校准组件采用相位内插器和模拟延迟线来调整辅助子ADC，使辅助子ADC能够排列到采样阵列的任何一个采样时刻。校准组件将辅助信号与子ADC信号进行比较，根据比较结果确定子ADC路径之间的路径差异，并校准子ADC和子ADC路径以减少路径差异以减轻数字中的失真通过组合由阵列中的子ADC产生的数字子流产生的流。

5. 发明授权

US09397867B1 Clock phase adaptation for precursor ISI reduction 有权
标题翻译：用于前体ISI减少的时钟相位适应
公开(公告)号：US09397867B1
公开(公告)日：2016-07-19
申请号：US14619952
申请日：2015-02-11
申请人： Applied Micro Circuits Corporation
发明人： Yehuda Azenkot , Guy Jacque Fortier
IPC分类号： H04L25/03 , H04L7/00
CPC分类号： H04L25/03019 , H04L7/0025 , H04L7/0062 , H04L2025/03592
摘要： Systems and methods of mitigating precursor ISIs for communication channels having time-variant precursor channel responses using digital circuit designs. A phase adaptation circuit is utilized in a receiver and configured to generate a phase control signal responsive to an input signal and based on the current precursor channel response. The phase control signal controls the phase shift of a recovered clock to a position where the precursor ISI at h(−1) is minimized. The phase control signal corresponds to a “feed-forward equalization (FFE) first tap weight” obtained via a digital least-mean-square (LMS) process.
摘要翻译：用于使用数字电路设计具有时变先驱信道响应的通信信道的前体ISI的系统和方法。在接收机中使用相位自适应电路，并且被配置为响应于输入信号并且基于当前前置信道响应产生相位控制信号。相位控制信号将恢复的时钟的相移控制在h（-1）处的前体ISI最小化的位置。相位控制信号对应于通过数字最小均方（LMS）处理获得的“前馈均衡（FFE）第一抽头权重”。

6. 发明授权

US09385696B1 Generating a pulse clock signal based on a first clock signal and a second clock signal 有权
标题翻译：基于第一时钟信号和第二时钟信号产生脉冲时钟信号
公开(公告)号：US09385696B1
公开(公告)日：2016-07-05
申请号：US14497629
申请日：2014-09-26
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Arun Jangity
IPC分类号： G06F1/04 , H03K3/017 , H03K5/05 , H03K3/037
CPC分类号： H03K5/05 , H03K3/037
摘要： Various aspects provide for generating a clock signal for a hold latch. A latch pulse generator generates a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component. A hold latch component receives the pulse clock signal generated by the latch pulse generator and generates a data signal that is transmitted to the second flip-flop component.
摘要翻译：各种方面提供用于产生用于保持锁存器的时钟信号。锁存脉冲发生器基于与第一触发器组件相关联的第一时钟信号和与第二触发器组件相关联的第二时钟信号产生脉冲时钟信号。保持锁存器组件接收由锁存脉冲发生器产生的脉冲时钟信号，并产生传输到第二触发器部件的数据信号。

7. 发明授权

US09367454B2 Address index recovery using hash-based exclusive or 有权
标题翻译：地址索引恢复使用基于散列的独占或
公开(公告)号：US09367454B2
公开(公告)日：2016-06-14
申请号：US13967607
申请日：2013-08-15
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Kjeld Svendsen
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0802 , G06F12/0893 , G06F12/0895 , Y02D10/13
摘要： Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.
摘要翻译：提供了便于在电子设备中检索散列索引的系统和方法。该系统包含一个寻址组件，它根据排他或身份生成散列索引。寻址组件可以根据标签值检索散列索引。因此，可以减少所需的存储区域，并且电子设备可以更有效率。

8. 发明申请

US20160020978A1 SYSTEM AND METHOD FOR MONITORING ENCODED SIGNALS IN A NETWORK 有权
标题翻译：用于监控网络中编码信号的系统和方法
公开(公告)号：US20160020978A1
公开(公告)日：2016-01-21
申请号：US13762589
申请日：2013-02-08
申请人： Dimitrios Giannakopoulos , Ben Brown
发明人： Dimitrios Giannakopoulos , Ben Brown
IPC分类号： H04L12/26
CPC分类号： H04L43/12 , H04L43/0847
摘要： Various aspects provide for non-intrusively monitoring a network system. A multiplexing component is configured to receive a plurality of first encoded signals and generate a plurality of second encoded signals. The plurality of second encoded signals contain a different data rate and a different number of network lanes than the plurality of first encoded signals. A monitoring component is configured to identify a block location for repeating blocks and an alignment marker in each of the plurality of first encoded signals and/or the plurality of second encoded signals. The monitoring component can also be configured to identify one or more defects, identify error information and/or determine one or more skew values associated with the plurality of first encoded signals and/or the plurality of second encoded signals.
摘要翻译：各种方面提供非侵入式监控网络系统。复用分量被配置为接收多个第一编码信号并产生多个第二编码信号。多个第二编码信号包含与多个第一编码信号不同的数据速率和不同数量的网络通道。监视组件被配置为识别重复块的块位置和多个第一编码信号和/或多个第二编码信号中的每一个中的对准标记。监视组件还可以被配置为识别一个或多个缺陷，识别错误信息和/或确定与多个第一编码信号和/或多个第二编码信号相关联的一个或多个偏斜值。

9. 发明申请

US20150317158A1 IMPLEMENTATION OF LOAD ACQUIRE/STORE RELEASE INSTRUCTIONS USING LOAD/STORE OPERATION WITH DMB OPERATION 审中-公开
标题翻译：使用DMB操作的负载/存储操作实现负载采集/存储释放指令
公开(公告)号：US20150317158A1
公开(公告)日：2015-11-05
申请号：US14243949
申请日：2014-04-03
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Matthew Ashcraft , Christopher Nelson
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834
摘要： A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.
摘要翻译：提供了一种用于简化在简化指令集计算（RISC）中使用的负载获取和存储释放语义的系统和方法。将语义转换为微操作或用于实现复杂机器指令的低级指令，可以避免执行复杂的新内存操作。使用一个或多个数据存储器屏障操作结合加载和存储操作可以提供足够的顺序，因为数据存储器屏障确保在执行后续指令之前执行和完成先前的指令。

10. 发明授权

US09142286B2 Integrated circuit memory device with read-disturb control 有权
标题翻译：具有读干扰控制的集成电路存储器件
公开(公告)号：US09142286B2
公开(公告)日：2015-09-22
申请号：US13863208
申请日：2013-04-15
申请人： Applied Micro Circuits Corporation
发明人： Jason T Su , Jitendra Khare
IPC分类号： G11C8/00 , G11C11/419 , G11C7/02 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C7/02 , G11C8/08 , G11C11/418
摘要： A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.
摘要翻译：装置（例如，诸如静态随机存取存储装置的集成电路存储装置）包括字线驱动器。每个字线驱动器包括经由共享线耦合到节点的上拉设备。预充电装置耦合在电源和节点之间。控制用于所选字线驱动器的预充电装置和上拉装置，以允许电源为节点充电，然后允许存储在节点中的电荷流入对应于所选字线驱动器的字线。

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