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1. 发明授权

US09496019B2 CMOS analog memories utilizing ferroelectric capacitors 有权
标题翻译：使用铁电电容器的CMOS模拟存储器
公开(公告)号：US09496019B2
公开(公告)日：2016-11-15
申请号：US15072292
申请日：2016-03-16
申请人： Radiant Technologies, Inc.
发明人： Joseph T. Evans, Jr. , Calvin B. Ward
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2273 , G11C11/2275 , G11C11/5657
摘要： A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.
摘要翻译：公开了一种存储单元和由该存储单元构成的存储器。根据本发明的存储器包括铁电电容器，电荷源和读电路。电荷源接收要存储在铁电电容器中的数据值。电荷源将数据值转换为存储在铁电电容器中的剩余电荷，并使残留电荷存储在铁电体电容器中。读取电路确定存储在铁电体电容器中的电荷。数据值具有三个不同的可能状态，并且所确定的电荷具有多于三个确定的值。存储器还包括使铁电电容器进入预定的已知参考偏振状态的复位电路。

2. 发明申请

US20160196862A1 CMOS Analog Memories Utilizing Ferroelectric Capacitors 审中-公开
公开(公告)号：US20160196862A1
公开(公告)日：2016-07-07
申请号：US15072292
申请日：2016-03-16
申请人： Radiant Technologies, Inc.
发明人： Joseph T. Evans, JR. , Calvin B. Ward
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2273 , G11C11/2275 , G11C11/5657
摘要： A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

3. 发明授权

US08942022B2 Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption 有权
标题翻译：嵌入式非易失性存储器电路，用于在电源中断期间实现逻辑功能
公开(公告)号：US08942022B2
公开(公告)日：2015-01-27
申请号：US14338153
申请日：2014-07-22
申请人： Radiant Technologies, Inc.
发明人： Joseph T. Evans
IPC分类号： G11C11/22
CPC分类号： H03K19/0008 , G11C7/1006 , G11C11/22 , G11C11/221 , G11C11/2297 , H03K19/096
摘要： A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.
摘要翻译：公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。开关被定位成在第一和第二AML电源触点之间提供电力时防止AML的状态改变。在本发明的一个方面，电路可以包括与AML输入或AML输出中的另一个串联的第二开关和与AML输入或AML输出串联的锁存器。锁存器的定位使得AML输出和AML输入之间不存在直接回路。

4. 发明授权

US08760907B2 Analog memories utilizing ferroelectric capacitors 有权
标题翻译：使用铁电电容器的模拟存储器
公开(公告)号：US08760907B2
公开(公告)日：2014-06-24
申请号：US12956845
申请日：2010-11-30
申请人： Joseph T. Evans, Jr. , Calvin B. Ward
发明人： Joseph T. Evans, Jr. , Calvin B. Ward
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.
摘要翻译：公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。

5. 发明授权

US6074885A Lead titanate isolation layers for use in fabricating PZT-based capacitors and similar structures 失效
标题翻译：用于制造基于PZT的电容器和类似结构的钛酸铅绝缘层
公开(公告)号：US6074885A
公开(公告)日：2000-06-13
申请号：US978308
申请日：1997-11-25
申请人： Leonard L. Boyer , Joseph T. Evans, Jr. , Naomi B. Velasquez
发明人： Leonard L. Boyer , Joseph T. Evans, Jr. , Naomi B. Velasquez
IPC分类号： H01L21/02 , H01L29/94 , H01L21/314
CPC分类号： H01L28/55 , H01L28/60
摘要： A method for constructing a device having a bottom electrode in contact with a layer of a ferroelectric dielectric material. In the method of the present invention, a layer of a field ferroelectric material is deposited on a substrate and etched to form a trench in which the bottom electrode is constructed. The bottom electrode is then deposited and a layer of the ferroelectric dielectric material is deposited over the bottom electrode and at least a portion of the field ferroelectric material. The ferroelectric layers are deposited in a perovskite state. These layers are etched back to the substrate in those areas that are outside of the device.
摘要翻译：一种用于构造具有与铁电介质材料层接触的底部电极的器件的方法。在本发明的方法中，将场强铁电材料层沉积在衬底上并被蚀刻以形成其中构成底电极的沟槽。然后沉积底部电极，并且铁电介质材料层沉积在底部电极和场致密铁电材料的至少一部分上。铁电层以钙钛矿状态沉积。这些层在设备外部的那些区域被回蚀刻到基底。

6. 发明授权

US5614438A Method for making LSCO stack electrode 失效
标题翻译： LSCO堆叠电极的制造方法
公开(公告)号：US5614438A
公开(公告)日：1997-03-25
申请号：US405216
申请日：1995-03-15
申请人： Joseph T. Evans, Jr. , Leonard Boyer
发明人： Joseph T. Evans, Jr. , Leonard Boyer
IPC分类号： H01L21/28 , H01L21/02 , H01L21/822 , H01L27/04 , H01L21/44
CPC分类号： H01L28/60 , H01L28/55 , Y10S148/014 , Y10S148/10
摘要： A method for making an improved LSCO stack in the generation of platinum features on the surface of a substrate. The method provides an inexpensive means for depositing and etching LSCO material in the construction of small platinum features. The method comprises sputtering of the LSCO material and utilizing a photoresist mask to pattern the LSCO in accordance with the platinum features. The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.
摘要翻译：一种在衬底表面上产生铂特征的改进的LSCO堆叠的方法。该方法提供了用于沉积和蚀刻LSCO材料以构造小铂特征的廉价方法。该方法包括溅射LSCO材料并利用光刻胶掩模来根据铂的特征对LSCO进行图案化。通过在室温下溅射LSCO来克服与LSCO在铂上的高温沉积相关的问题和费用及其蚀刻。

7. 发明授权

US10020042B2 CMOS analog memories utilizing ferroelectric capacitors 有权
公开(公告)号：US10020042B2
公开(公告)日：2018-07-10
申请号：US15271145
申请日：2016-09-20
申请人： Radiant Technologies, Inc.
发明人： Joseph T. Evans, Jr. , Calvin B. Ward
IPC分类号： G11C11/22 , G11C11/56
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2273 , G11C11/2275 , G11C11/5657
摘要： A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

8. 发明申请

US20170011789A1 CMOS Analog Memories Utilizing Ferroelectric Capacitors 审中-公开
标题翻译：使用铁电电容的CMOS模拟记忆体
公开(公告)号：US20170011789A1
公开(公告)日：2017-01-12
申请号：US15271145
申请日：2016-09-20
申请人： Radiant Technologies, Inc. , Radiant Technologies, Inc.
发明人： Joseph T. Evans, JR. , Calvin B. Ward
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2273 , G11C11/2275 , G11C11/5657
摘要： A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.
摘要翻译：公开了一种存储单元和由该存储单元构成的存储器。根据本发明的存储器包括铁电电容器，电荷源和读取电路。电荷源接收要存储在铁电电容器中的数据值。电荷源将数据值转换为存储在铁电电容器中的剩余电荷，并使残留电荷存储在铁电体电容器中。读取电路确定存储在铁电体电容器中的电荷。数据值具有三个不同的可能状态，并且所确定的电荷具有多于三个确定的值。存储器还包括使铁电电容器进入预定的已知参考偏振状态的复位电路。

9. 发明授权

US09269416B2 Non-volatile counter utilizing a ferroelectric capacitor 有权
标题翻译：利用铁电电容器的非易失性计数器
公开(公告)号：US09269416B2
公开(公告)日：2016-02-23
申请号：US14160343
申请日：2014-01-21
申请人： Radiant Technologies, Inc.
发明人： Joseph T. Evans, Jr.
IPC分类号： G11C11/22
CPC分类号： G11C11/2297 , G11C11/221 , G11C11/2273
摘要： A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.
摘要翻译：公开了可以包括多个计数级的计数器。每个计数级包括由第一和第二极化状态表征的铁电电容器，可变阻抗元件，复位和计数端口以及检测器。可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗，铁电电容器连接在控制端子和第一开关端子之间。耦合到控制端子的复位信号使得铁电电容器在第一偏振状态下被极化。计数端口被配置为接收待计数的脉冲，计数端口通过导电负载连接到第一开关端子。如果计数端口接收到其中一个脉冲，则第一端子上的电位超过阈值时，检测器产生计数完成信号。

10. 发明授权

US08565000B2 Variable impedance circuit controlled by a ferroelectric capacitor 有权
标题翻译：可变阻抗电路由铁电电容控制
公开(公告)号：US08565000B2
公开(公告)日：2013-10-22
申请号：US13223815
申请日：2011-09-01
申请人： Joseph Tate Evans, Jr.
发明人： Joseph Tate Evans, Jr.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.
摘要翻译：公开了一种包括铁电电容器，可变阻抗元件和导电负载的存储单元。特征在于第一和第二极化状态的铁电电容器连接在控制端子和第一开关端子之间。可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗。导电负载连接在第一电源端子和第一开关端子之间。第二开关端子连接到第二电源端子。当在第一和第二电源端子之间施加电位差时，第一开关端子上的电位以由铁电体电容器的极化状态确定的方式变化。

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