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1. 发明授权

US09324825B2 Manufacturing method of a graphene-based electrochemical sensor, and electrochemical sensor 有权
公开(公告)号：US09324825B2
公开(公告)日：2016-04-26
申请号：US13917379
申请日：2013-06-13
申请人： STMicroelectronics S.r.l.
发明人： Corrado Accardi , Stella Loverso , Sebastiano Ravesi , Noemi Graziana Sparta
IPC分类号： G01N27/403 , H01L29/66 , G01N27/414 , B01L3/00
CPC分类号： G01N27/414 , B01L3/502707 , H01L29/1606 , H01L29/66 , H01L29/66053
摘要： A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure.

2. 发明授权

US09184276B2 Method and apparatus for manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法和装置
公开(公告)号：US09184276B2
公开(公告)日：2015-11-10
申请号：US13502976
申请日：2011-02-25
申请人： Takeyoshi Masuda , Keiji Wada , Satomi Itoh , Toru Hiyoshi
发明人： Takeyoshi Masuda , Keiji Wada , Satomi Itoh , Toru Hiyoshi
IPC分类号： H01L21/311 , H01L29/78 , H01L21/04 , H01L29/66 , H01L21/02 , H01L29/16
CPC分类号： H01L29/7802 , H01L21/02057 , H01L21/02236 , H01L21/02301 , H01L21/0445 , H01L21/049 , H01L29/1608 , H01L29/66053 , H01L29/66068
摘要： A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.
摘要翻译：一种制造SiC半导体器件的方法包括以下步骤：在SiC半导体的第一表面上形成第一氧化物膜，去除第一氧化物膜，以及在第二表面上形成构成SiC半导体器件的第二氧化膜，去除SiC半导体中第一氧化膜的结果。在除去第一氧化物膜的步骤和形成第二氧化物膜的步骤之间，将SiC半导体布置在从环境气氛切断的气氛中。

3. 发明申请

US20150084067A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150084067A1
公开(公告)日：2015-03-26
申请号：US14458584
申请日：2014-08-13
申请人： Kabushiki Kaisha Toshiba
发明人： Ryosuke IIJIMA , Yukio NAKABAYASHI , Tatsuo SHIMIZU
IPC分类号： H01L29/66 , H01L29/36 , H01L21/02 , H01L29/16
CPC分类号： H01L29/66477 , H01L21/02238 , H01L21/049 , H01L21/28229 , H01L21/28255 , H01L21/302 , H01L21/32105 , H01L29/0649 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/36 , H01L29/66053 , H01L29/66068 , H01L29/66613 , H01L29/66621 , H01L29/7395 , H01L29/7802 , H01L29/7813
摘要： The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of-the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film.
摘要翻译：该实施例的半导体器件包括：第一导电类型SiC的第一区域; 第一导电型SiC的第二区域，第二区域的第一导电类型的杂质浓度低于第一区域的第一导电类型的杂质浓度; 设置在所述第一区域和所述第二区域之间的第二导电型SiC的第三区域; 设置在所述第一，第二和第三区域的表面上的Si层，所述第三区域上的所述Si层的厚度比所述第二区域上的所述Si层的厚度厚; 设置在所述Si层上的栅极绝缘膜; 以及设置在栅极绝缘膜上的日期电极。

4. 发明授权

US08952481B2 Super surge diodes 有权
标题翻译：超级浪涌二极管
公开(公告)号：US08952481B2
公开(公告)日：2015-02-10
申请号：US13681993
申请日：2012-11-20
申请人： Cree, Inc.
发明人： Qingchun Zhang , Jennifer Duc
IPC分类号： H01L29/47 , H01L21/28 , H01L29/872 , H01L29/66 , H01L29/16 , H01L29/06
CPC分类号： H01L29/1608 , H01L29/0619 , H01L29/47 , H01L29/66053 , H01L29/6606 , H01L29/872
摘要： The present disclosure relates to a semiconductor device having a Schottky contact that provides both super surge capability and low reverse-bias leakage current. In one preferred embodiment, the semiconductor device is a Schottky diode and even more preferably a Silicon Carbide (SiC) Schottky diode. However, the semiconductor device may more generally be any type of semiconductor device having a Schottky contact such as, for example, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).
摘要翻译：本发明涉及一种具有提供超级浪涌能力和低反向偏置漏电流的肖特基接触的半导体器件。在一个优选实施例中，半导体器件是肖特基二极管，甚至更优选碳化硅（SiC）肖特基二极管。然而，半导体器件可以更通常地是具有肖特基接触的任何类型的半导体器件，例如金属氧化物半导体场效应晶体管（MOSFET）。

5. 发明申请

US20140252468A1 Engineered Source/Drain Region for N-Type MOSFET 有权
标题翻译： N型MOSFET的工程源/漏区
公开(公告)号：US20140252468A1
公开(公告)日：2014-09-11
申请号：US13788524
申请日：2013-03-07
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
发明人： Wei-Yuan Lu , Lilly Su , Chun-Hung Huang , Chii-Horng Li , Jyh-Huei Chen
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L21/823418 , H01L29/0843 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/1608 , H01L29/165 , H01L29/66053 , H01L29/6606 , H01L29/66068 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66689 , H01L29/7834 , H01L29/7842 , H01L29/7848
摘要： Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.
摘要翻译：具有场效应晶体管的集成电路器件具有包括第一和第二层的源区和漏区。第一层形成在通道区域的平面之下。第一层包括具有小于硅的晶格结构的掺杂硅和碳。第二层形成在第一层上并且在沟道区的平面上方上升。第二层由包括掺杂的外延生长的硅的材料形成。第二层的碳原子分数小于第一层的一半。第一层形成在通道区域的表面下方至少10nm的深度。该结构有助于形成非常浅的结的源极和漏极扩展区域。这些装置提供具有低电阻的源和漏极，同时抵抗短沟道效应。

6. 发明授权

US08785945B2 SiC bipolar junction transistor with overgrown emitter 有权
标题翻译：具有超长发射极的SiC双极结型晶体管
公开(公告)号：US08785945B2
公开(公告)日：2014-07-22
申请号：US13688067
申请日：2012-11-28
申请人： Fairchild Semiconductor Corporation
发明人： Andrei Konstantinov
IPC分类号： H01L29/73
CPC分类号： H01L29/73 , H01L29/045 , H01L29/06 , H01L29/0611 , H01L29/1004 , H01L29/1608 , H01L29/66053 , H01L29/66068 , H01L29/66234 , H01L29/7325
摘要： New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion.
摘要翻译：提供了碳化硅（SiC）双极结晶体管（BJT）的新设计和制造这种SiC BJT的新方法。 SiC BJT可以包括集电极区域，基极区域和发射极区域，其中集电极区域，基极区域和发射极区域被布置为堆叠。发射极区域可以形成由设置在堆叠上的外侧壁限定的升高结构。基区可以具有与发射极区接口并限定本征基区的部分。本征基极区域可以包括第一部分，该第一部分通过基极区域的第二部分横向间隔离发射极区域的外侧壁，该第二部分具有高于第一部分的掺杂剂剂量的掺杂剂剂量。

7. 发明申请

US20190207001A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20190207001A1
公开(公告)日：2019-07-04
申请号：US16299025
申请日：2019-03-11
申请人： Renesas Electronics Corporation
发明人： Yuya ABIKO , Natsuo YAMAGUCHI , Satoshi EGUCHI
IPC分类号： H01L29/10 , H01L21/265 , H01L29/06 , H01L29/16 , H01L29/78 , H01L21/308 , H01L29/40 , H01L21/02 , H01L29/66 , H01L29/739
CPC分类号： H01L29/1095 , H01L21/02529 , H01L21/26586 , H01L21/308 , H01L29/0634 , H01L29/1608 , H01L29/404 , H01L29/66053 , H01L29/66068 , H01L29/66712 , H01L29/66734 , H01L29/7395 , H01L29/7802 , H01L29/7813
摘要： In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

8. 发明申请

US20180033703A1 SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20180033703A1
公开(公告)日：2018-02-01
申请号：US15552863
申请日：2016-01-21
申请人： Sumitomo Electric Industries, Ltd.
发明人： Tsubasa HONKE , Kyoko OKITA
IPC分类号： H01L21/66 , C23C14/34 , C23C14/58 , C30B29/36 , B24C1/08 , C30B33/02 , H01L21/027 , H01L21/306 , H01L29/66 , C23C14/06 , C30B25/20
CPC分类号： H01L22/20 , B24C1/08 , C23C14/0682 , C23C14/185 , C23C14/34 , C23C14/5806 , C23C16/325 , C30B25/186 , C30B25/20 , C30B29/36 , C30B31/20 , C30B33/02 , H01L21/02013 , H01L21/02024 , H01L21/027 , H01L21/265 , H01L21/304 , H01L21/30625 , H01L22/12 , H01L29/045 , H01L29/1608 , H01L29/66053 , H01L29/66068 , H01L29/7395 , H01L29/7802 , H01L29/8083 , H01L29/872
摘要： A silicon carbide single crystal substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface includes a central square region and an outer square region. When viewed in a thickness direction, each of the central square region and the outer square region has a side having a length of 15 mm. The first main surface has a maximum diameter of not less than 100 mm. The silicon carbide single crystal substrate has a TTV of not more than 5 μm. A value obtained by dividing a LTIR in the central square region by a LTV in the central square region is not less than 0.8 and not more than 1.2. A value obtained by dividing a LTV in the outer square region by the LTV in the central square region is not less than 1 and not more than 3.

9. 发明授权

US09515176B2 Silicon carbide bipolar junction transistor including shielding regions 有权
标题翻译：碳化硅双极结晶体管包括屏蔽区域
公开(公告)号：US09515176B2
公开(公告)日：2016-12-06
申请号：US13938006
申请日：2013-07-09
申请人： Fairchild Semiconductor Corporation
发明人： Andrei Konstantinov
IPC分类号： H01L29/66 , H01L29/73 , H01L29/04 , H01L29/10 , H01L29/16 , H01L29/732 , H01L29/06
CPC分类号： H01L29/73 , H01L29/045 , H01L29/06 , H01L29/0611 , H01L29/1004 , H01L29/1608 , H01L29/66053 , H01L29/66068 , H01L29/66234 , H01L29/7325
摘要： A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type.
摘要翻译：提供了碳化硅（SiC）双极结型晶体管（BJT）和制造这种SiC BJT的方法。 SiC BJT可以包括具有第一导电类型的集电极区域，具有与第一导电类型相反的第二导电类型的基极区域和具有第一导电类型的发射极区域，集电极区域，基极区域和发射极区域是排列成堆叠。所述发射极区限定至少部分地由所述堆叠顶部的外侧壁限定的升高的结构。该基极区域具有由发射极区域覆盖的部分并且限定本征基极区域，其中本征基极区域包括从发射极区域延伸到集电极区域的部分。 SiC BJT可以包括具有第二导电类型的第一屏蔽区域和第二屏蔽区域。

10. 发明申请

US20160116432A1 MANUFACTURING METHOD OF A GRAPHENE-BASED ELECTROCHEMICAL SENSOR, AND ELECTROCHEMICAL SENSOR 审中-公开
公开(公告)号：US20160116432A1
公开(公告)日：2016-04-28
申请号：US14986132
申请日：2015-12-31
申请人： STMICROELECTRONICS S.R.L.
发明人： Corrado ACCARDI , Stella LOVERSO , Sebastiano RAVESI , Noemi Graziana SPARTA
IPC分类号： G01N27/414 , H01L29/16
CPC分类号： G01N27/414 , B01L3/502707 , H01L29/1606 , H01L29/66 , H01L29/66053
摘要： A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure.

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