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1. 发明申请

US20180041228A1 PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME 审中-公开
公开(公告)号：US20180041228A1
公开(公告)日：2018-02-08
申请号：US15553910
申请日：2016-02-25
申请人： Electronics and Telecommunications Research Institute
发明人： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
IPC分类号： H03M13/15 , H03M13/27 , H03M13/11
CPC分类号： H03M13/152 , H03M13/116 , H03M13/1162 , H03M13/1165 , H03M13/253 , H03M13/255 , H03M13/271 , H03M13/2778 , H03M13/2906 , H03M13/618 , H03M13/6362 , H03M13/6393 , H03M13/6552
摘要： A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

2. 发明申请

US20170104499A1 EFFICIENT LDPC ENCODER FOR IRREGULAR CODE 审中-公开
公开(公告)号：US20170104499A1
公开(公告)日：2017-04-13
申请号：US15018682
申请日：2016-02-08
申请人： SK Hynix Inc.
发明人： Wei-Hao Yuan , Lingqi Zeng , Aman Bhatia , Johnson Yen
IPC分类号： H03M13/29 , G06F11/10 , G11C29/52 , H03M13/11
CPC分类号： H03M13/2909 , G06F11/1068 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/116 , H03M13/1162 , H03M13/1177 , H03M13/118 , H03M13/1185 , H03M13/1197 , H03M13/611 , H03M13/616 , H04L1/0009 , H04L1/0041 , H04L1/0057
摘要： A first memory location stores circulant contents of portions A, C, E, and B of a parity check matrix H. A second memory location stores circulant column counts of the portions A, C, E, and B. A third memory location stores a dense matrix equal to (ET−1B+D)−1, where T is an identity matrix and D and T are also portions of the parity check matrix H. First and second parity information is generated in response to receiving information data. Generating the first and second parity information includes accessing the circular content of the portions A, C, E, and B of a parity check matrix H and accessing the circulant column counts of the portions A, C, E, and B.

3. 发明授权

US09391647B2 Decoder and decoding method thereof for min-sum algorithm low density parity-check code 有权
标题翻译：用于最小和算法低密度奇偶校验码的解码器及其解码方法
公开(公告)号：US09391647B2
公开(公告)日：2016-07-12
申请号：US14335392
申请日：2014-07-18
申请人： STORART TECHNOLOGY CO. LTD.
发明人： Jui-Hui Hung , Chih-Nan Yen
IPC分类号： H03M13/00 , H03M13/11 , H03M13/37 , H04L1/00
CPC分类号： H03M13/6566 , H03M13/11 , H03M13/1102 , H03M13/1105 , H03M13/1114 , H03M13/112 , H03M13/1122 , H03M13/1131 , H03M13/114 , H03M13/1162 , H03M13/3746 , H04L1/0061
摘要： The present disclosure illustrates a decoder for min-sum algorithm low density parity-check code. The decoder is adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes a plurality of calculation units, and the memory includes a plurality of memory units. Each calculation unit includes a check node unit, a first message re-constructor and a second message re-constructor. The calculation module divides the coding data into several data groups, and the data group is calculated by each calculation unit. The check node unit generates a stored-form of a calculating result by calculating the respective data group. The calculating result is reconstructed by the first message re-constructor and summed with the following data group. The memory unit stores the respective calculating result generated from the calculation unit.
摘要翻译：本公开示出了用于最小和算法低密度奇偶校验码的解码器。解码器适于对具有位节点和校验节点的编码数据进行解码。解码器包括计算模块和存储器。计算模块包括多个计算单元，并且存储器包括多个存储器单元。每个计算单元包括校验节点单元，第一消息重构器和第二消息重建器。计算模块将编码数据分成若干数据组，并由每个计算单元计算数据组。校验节点单元通过计算各个数据组生成计算结果的存储形式。计算结果由第一个消息重建器重建，并与以下数据组相加。存储单元存储从计算单元生成的相应的计算结果。

4. 发明授权

US09048867B2 Shift register-based layered low density parity check decoder 有权
标题翻译：基于移位寄存器的分层低密度奇偶校验解码器
公开(公告)号：US09048867B2
公开(公告)日：2015-06-02
申请号：US13898685
申请日：2013-05-21
申请人： LSI Corporation
发明人： Dan Liu , Qi Zuo , Chung-Li Wang , Zongwang Li , Lei Wang
IPC分类号： H03M13/11 , H04L1/00
CPC分类号： H03M13/1105 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1122 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1162 , H03M13/1171 , H03M13/1174 , H03M13/6331 , H03M13/6505 , H03M13/658 , H03M13/6583 , H04L1/005
摘要： An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.
摘要翻译：用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

5. 发明申请

US20150143194A1 REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM 有权
标题翻译：减少复杂非二进制LDPC解码算法
公开(公告)号：US20150143194A1
公开(公告)日：2015-05-21
申请号：US14607039
申请日：2015-01-27
申请人： HGST Netherlands B.V.
发明人： Majid NEMATI ANARAKI , Xinde Hu , Richard D. Barndt
IPC分类号： H03M13/11
CPC分类号： H03M13/458 , H03M13/05 , H03M13/1105 , H03M13/1111 , H03M13/1122 , H03M13/1128 , H03M13/114 , H03M13/1162 , H03M13/1171 , H03M13/255 , H03M13/615 , H03M13/6505
摘要： Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.
摘要翻译：提供了在数据缓冲器上可操作以表示多个可变节点和多个校验节点的解码逻辑。对于相应的一个变量节点，从与变量节点相关联的置信向量中选择向量分量。使用校验节点中的相应一个，基于来自一个或多个其他向量的一个或多个其他向量分量和对应于一个或多个其它向量分量的一个或多个向量索引来计算校验节点返回值。然后基于校验节点返回值和校验节点返回值的索引来更新置信向量，并且基于主要位置的位置确定与相应一个变量节点相关联的存储器单元的当前状态在更新的置信向量内的多个向量分量。

6. 发明申请

US20140351671A1 Shift Register-Based Layered Low Density Parity Check Decoder 有权
标题翻译：基于移位寄存器的分层低密度奇偶校验解码器
公开(公告)号：US20140351671A1
公开(公告)日：2014-11-27
申请号：US13898685
申请日：2013-05-21
申请人： LSI Corporation
发明人： Dan Liu , Qi Zuo , Chung-Li Wang , Zongwang Li , Lei Wang
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1122 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1162 , H03M13/1171 , H03M13/1174 , H03M13/6331 , H03M13/6505 , H03M13/658 , H03M13/6583 , H04L1/005
摘要： An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.
摘要翻译：用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

7. 发明申请

US20140344639A1 APPARATUS AND METHOD FOR CODING/DECODING BLOCK LOW DENSITY PARITY CHECK CODE IN A MOBILE COMMUNICATION SYSTEM 审中-公开
标题翻译：移动通信系统中编码/解码块低密度奇偶校验码的装置和方法
公开(公告)号：US20140344639A1
公开(公告)日：2014-11-20
申请号：US14256288
申请日：2014-04-18
申请人： Samsung Electronics Co., Ltd.
发明人： Gyu-Bum KYUNG , Hong-Sil JEONG , Jae-Yoel KIM , Sung-Eun PARK , Kyeong-Cheol YANG , Se-Ho MYUNG
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1102 , H03M13/1151 , H03M13/1162 , H03M13/1171 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/1194
摘要： A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.
摘要翻译：提供了一种用于处理块低密度奇偶校验（LDPC）码的系统和方法。该系统包括：使用奇偶校验矩阵解码块LDPC码的解码装置，奇偶校验矩阵包括信息部分和奇偶校验部分，奇偶校验部分包括包括多个第一置换矩阵的第一部分（B）包括第二置换矩阵的第二部分（D），包括在第三部分内对角排列的多个单位矩阵（I）的第三部分（T）和布置在多个单位矩阵之下的多个第三置换矩阵，以及第四部分（E）包括第四置换矩阵。

8. 发明申请

US20120260144A1 ENCODING AND DECODING TECHNIQUES USING LOW-DENSITY PARITY CHECK CODES 有权
标题翻译：使用低密度奇偶校验码编码和解码技术
公开(公告)号：US20120260144A1
公开(公告)日：2012-10-11
申请号：US13083341
申请日：2011-04-08
申请人： Chandra C. Varanasi , Guiqiang Dong
发明人： Chandra C. Varanasi , Guiqiang Dong
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/118 , G06F11/10 , H03M13/1151 , H03M13/1162 , H03M13/1165 , H03M13/1174 , H03M13/1182 , H03M13/611 , H03M13/616 , H04L1/0045 , H04L1/0057
摘要： Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括用于对消息信息进行编码的装置和方法。这样的装置和方法可以包括使用低密度奇偶校验（LDPC）码的奇偶校验矩阵来生成具有上三角子矩阵的第一矩阵。如果上三角形子矩阵的总行数等于奇偶校验矩阵的等级，则可以基于第一矩阵来生成用于编码消息信息的奇偶校验信息。如果上三角形子矩阵的总行数小于奇偶校验矩阵的秩，则可以对第一矩阵的第二子矩阵执行三角化操作以生成第二矩阵。可以基于第二矩阵来生成用于编码消息信息的奇偶校验信息。描述包括附加装置和方法的其它实施例。

9. 发明授权

US08205142B2 Error correction coding method and device 有权
标题翻译：纠错编码方法及装置
公开(公告)号：US08205142B2
公开(公告)日：2012-06-19
申请号：US12300412
申请日：2007-04-25
申请人： Norifumi Kamiya
发明人： Norifumi Kamiya
IPC分类号： G06F11/00
CPC分类号： H03M13/11 , G11B20/18 , H03M13/1151 , H03M13/116 , H03M13/1162 , H03M13/1168 , H03M13/611 , H03M13/617 , H03M13/6561
摘要： An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m−r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n−k1, n−k2, . . . , n−kr.
摘要翻译：使用低密度奇偶校验码的纠错编码方法包括：将要进行纠错编码处理的信息比特序列划分成（m-r）个第一块，每个第一块包括长度为n和r的比特序列包括具有长度k1，k2，...的各个比特序列的第二块块。。。，kr; 用于对（m-r）个第一块进行多项式乘法并输出具有长度为n的r个比特序列的第一算术运算; 以及第二算术运算，用于对第一运算结果的r个第二块和r个运算结果执行多项式除法和多项式乘法，并输出包括具有各自长度n-k1，n的冗余位序列的比特序列 -k2，。。，n-kr。

10. 发明申请

US20100269025A1 Method for error correction and error detection of binary data 有权
标题翻译：二进制数据的纠错和错误检测方法
公开(公告)号：US20100269025A1
公开(公告)日：2010-10-21
申请号：US12587419
申请日：2009-10-07
申请人： Xiao-Ming Chen , Oliver Theis , Marco Georgi
发明人： Xiao-Ming Chen , Oliver Theis , Marco Georgi
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1162 , H03M13/1105 , H03M13/17 , H03M13/2906 , H03M13/43
摘要： For algebraic single symbol error correction and detection, a method is proposed which achieves correcting single symbol errors at unknown positions within codewords, identifiying cases where multiple symbols within a codeword are uncorrectably corrupted, and identifying cases where a single symbol within a codeword is uncorrectably corrupted. The method comprises the steps of calculating a syndrome of a received word, splitting the syndrome into two parts, checking 3 integer weight quantities calculated from the two syndrome parts, converting the syndrome into a vector of integer valued “orthogonal bit error weights” associated to the received bits, and toggling those bits of the received word, where the associated “orthogonal bit error weight” is in the upper half of its possible value range.
摘要翻译：对于代数单符号纠错和检测，提出了一种方法，其实现了在码字内的未知位置处校正单个符号错误，识别码字内的多个符号是不可纠正的损坏的情况，以及识别码字内的单个符号是否被不可纠错地损坏的情况。该方法包括以下步骤：计算接收到的词的综合征，将所述综合征分为两部分，检查从所述两个综合征部分计算的3个整数权重量，将所述校正子转换为与所述校正子相关联的整数值“正交位错误权重”的向量接收到的比特，并且切换接收到的字的那些比特，其中相关联的“正交比特误差权重”在其可能的值范围的上半部分。

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