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1. 发明授权

US10009146B2 Polar code rate matching method and rate matching apparatus 有权
公开(公告)号：US10009146B2
公开(公告)日：2018-06-26
申请号：US15269553
申请日：2016-09-19
申请人： Huawei Technologies Co., Ltd.
发明人： Hui Shen , Bin Li , Jun Chen
IPC分类号： H04L1/00 , H03M13/27 , H04L1/18 , H03M13/13 , H03M13/00 , H04W28/14
CPC分类号： H04L1/0067 , H03M13/13 , H03M13/2739 , H03M13/6306 , H03M13/6362 , H04L1/0041 , H04L1/0057 , H04L1/0061 , H04L1/0068 , H04L1/0071 , H04L1/1812 , H04L1/1819 , H04L1/1835 , H04L1/1867 , H04W28/14
摘要： A Polar code rate matching method and a rate matching apparatus are disclosed. The method includes: dividing a system Polar code output by a Polar code encoder into system bits and parity bits; interleaving the system bits to obtain a first group of interleaved bits, and interleaving the parity bits to obtain a second group of interleaved bits; and determining a rate-matched output sequence based on the first group of interleaved bits and the second group of interleaved bits. System bits and parity bits are separately interleaved, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance, and ensuring reliability of data transmission.

2. 发明申请

US20180175967A1 METHOD FOR CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS THEREFOR 审中-公开
公开(公告)号：US20180175967A1
公开(公告)日：2018-06-21
申请号：US15580538
申请日：2015-06-10
申请人： LG ELECTRONICS INC.
发明人： Kwangseok NOH , Hyunsoo KO , Dongkyu KIM , Sangrim LEE , Hojae LEE
IPC分类号： H04L1/00 , H03M13/00 , H03M13/39
CPC分类号： H04L1/001 , H03M13/09 , H03M13/1194 , H03M13/23 , H03M13/2739 , H03M13/2778 , H03M13/2906 , H03M13/2957 , H03M13/35 , H03M13/353 , H03M13/3938 , H03M13/6513 , H04L1/00 , H04L1/0009 , H04L1/0025 , H04L1/0041 , H04L1/0065 , H04L1/0068 , H04L1/0071 , H04L1/0075 , H04L1/16 , H04L1/1867 , H04W4/06 , H04W4/40
摘要： The present invention relates to a method for performing channel encoding by a transmitting end in a wireless communication system. Particularly, the method comprises the steps of: transmitting, to a receiving end, a configuration indicating a plurality of channel coding configurations; performing channel encoding using a first channel coding configuration among the plurality of channel coding configurations; and performing reconfiguration from the first channel coding configuration to a second channel coding configuration according to a change in system requirements, wherein the plurality of channel coding configurations comprise channel coding configurations, each comprising at least one channel code concatenated differently according to the system requirements.

3. 发明申请

US20150026535A1 APPARATUS AND METHOD FOR GENERATING INTERLEAVER INDEX 有权
标题翻译：用于生成交换索引的装置和方法
公开(公告)号：US20150026535A1
公开(公告)日：2015-01-22
申请号：US14370571
申请日：2012-02-24
申请人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Jaehwan Kim
发明人： Jinsoup Joung , Joohyeong Lee , Jongho Lim , Jaehwan Kim
IPC分类号： H03M13/27
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/276 , H03M13/395 , H03M13/6561
摘要： Disclosed is an apparatus and a method for generating an internal interleaver index of a turbo encoder in parallel. There are effects of reducing the time spent for generating total indexes by generating indexes for a plurality of bits in parallel and improving the resource efficiency and the performance in the hardware implementation by calculating indexes for following bits through the use of an index calculated for a predetermined bit without the use of a multiplier and a divider.
摘要翻译：公开了并行地生成turbo编码器的内部交织器索引的装置和方法。通过使用针对预定的方式计算的索引来计算跟踪比特的索引，具有减少用于并行生成多个比特的索引并且提高资源效率和硬件实现中的性能来生成总索引的时间的效果位而不使用乘法器和分频器。

4. 发明授权

US08806290B2 Systems and methods for parallel dual-mode turbo decoders 有权
标题翻译：并行双模涡轮解码器的系统和方法
公开(公告)号：US08806290B2
公开(公告)日：2014-08-12
申请号：US13948772
申请日：2013-07-23
申请人： Intel Corporation
发明人： Tao Zhang , Yuan Li , Jianbin Zhu
IPC分类号： H03M13/00 , H03M13/27 , G06F11/10 , H03M13/39 , H03M13/29
CPC分类号： G06F11/10 , H03M13/271 , H03M13/2714 , H03M13/2739 , H03M13/2957 , H03M13/395 , H03M13/3972 , H03M13/6505 , H03M13/6525 , H03M13/6561
摘要： According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.
摘要翻译：根据一些实施例，提供了配置用于高速分组接入（HSPA）和长期演进（LTE）的turbo解码器，包括：多个最大后验（MAP）引擎; 由多个MAP引擎的MAP引擎访问的多个外部存储器组; 并且其中当所述turbo解码器以HSDPA模式操作时，所述多个非本征存储体被配置为使得在解码迭代的前半部分期间，MAP引擎能够从第二数据集读取第一数据集并将第二数据集写入到所述多个外部存储器组以自然行和列顺序排列，并且在解码迭代的后半段期间，MAP引擎能够以预定的行和列顺序从第二数据集读取和写入第四数据集到多个外部存储体根据使用读列缓冲器和写列缓冲器的交织器表。

5. 发明申请

US20130311852A1 Systems and Methods for Parallel Dual-Mode Turbo Decoders 有权
标题翻译：并行双模Turbo解码器的系统和方法
公开(公告)号：US20130311852A1
公开(公告)日：2013-11-21
申请号：US13948772
申请日：2013-07-23
申请人： Mindspeed
发明人： TAO ZHANG , YUAN LI , JIANBIN ZHU
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , H03M13/271 , H03M13/2714 , H03M13/2739 , H03M13/2957 , H03M13/395 , H03M13/3972 , H03M13/6505 , H03M13/6525 , H03M13/6561
摘要： According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.
摘要翻译：根据一些实施例，提供了配置用于高速分组接入（HSPA）和长期演进（LTE）的turbo解码器，包括：多个最大后验（MAP）引擎; 由多个MAP引擎的MAP引擎访问的多个外部存储器组; 并且其中当所述turbo解码器以HSDPA模式操作时，所述多个非本征存储体被配置为使得在解码迭代的前半部分期间，MAP引擎能够从第二数据集读取第一数据集并将第二数据集写入到所述多个外部存储器组以自然行和列顺序排列，并且在解码迭代的后半段期间，MAP引擎能够以预定的行和列顺序从第二数据集读取和写入第四数据集到多个外部存储体根据使用读列缓冲器和写列缓冲器的交织器表。

6. 发明申请

US20120047414A1 ADDRESS GENERATION APPARATUS AND METHOD FOR QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER 有权
标题翻译：地址生成装置和方法用于四元制多边形交织器
公开(公告)号：US20120047414A1
公开(公告)日：2012-02-23
申请号：US12892199
申请日：2010-09-28
申请人： SHUENN-GI LEE , CHUNG HSUAN WANG , WERN-HO SHEEN
发明人： SHUENN-GI LEE , CHUNG HSUAN WANG , WERN-HO SHEEN
IPC分类号： H03M13/05 , G06F11/08
CPC分类号： H03M13/2739 , H03M13/2764 , H03M13/2775
摘要： An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus.
摘要翻译：二次置换多项式（QPP）交织器的地址生成装置接收多个可配置参数，并使用多个QPP单元根据QPP函数＆Pgr计算并输出多个交织地址;（i）=（f1i + f2i2）mod k ，其中f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k-1，mod是模运算。多个QPP单元中的每一个是并行计算单元，并且并行地输出相应的交织器地址组，其中＆amp;（i）也是由该设备生成的第i个交织地址。

7. 发明申请

US20110307673A1 RECONFIGURABLE INTERLEAVER HAVING RECONFIGURABLE COUNTERS 有权
标题翻译：具有可重构计数器的可重新配置的交换机
公开(公告)号：US20110307673A1
公开(公告)日：2011-12-15
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： G06F12/06
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

8. 发明申请

US20110296285A1 WIRELESS COMMUNICATION APPARATUS 有权
标题翻译：无线通信设备
公开(公告)号：US20110296285A1
公开(公告)日：2011-12-01
申请号：US13147737
申请日：2009-12-10
申请人： Jifeng Li
发明人： Jifeng Li
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/258 , H03M13/256 , H03M13/2739 , H03M13/356 , H03M13/6356 , H04L1/0041 , H04L1/0059
摘要： Disclosed is a wireless communication apparatus in which reception precision characteristics are improved, by specially adapting the modulating processing in respect of the code words for each encoding system. A wireless communication apparatus (100) wherein an encoding processing section (120) includes a convolutional encoder that performs convolutional encoding of fixed information blocks made up of K bits. In code word partial sequences obtained on the basis of the head and tail in a fixed information block, a modulating section (130) maps bits, from bit groups constituting single symbols, to bits associated with groups having poor quality characteristics, prioritising systematic bits over parity bits. In this way, the reception quality characteristics in first code word partial sequences having good error characteristics is equalised. Consequently, since portions having poor reception quality characteristics are prevented from prominent appearance in the first code word partial sequence, the result is that the reception quality characteristics and system throughput can be improved.
摘要翻译：公开了通过特别适应每个编码系统的码字的调制处理，提高了接收精度特性的无线通信装置。一种无线通信装置（100），其中编码处理部分（120）包括对由K比特组成的固定信息块进行卷积编码的卷积编码器。在固定信息块中基于头部和尾部获得的码字部分序列中，调制部分（130）将来自构成单个符号的比特组的比特映射到与具有差的质量特性的组相关联的比特，将系统比特优先化奇偶校验位。以这种方式，具有良好误差特性的第一码字部分序列中的接收质量特性相等。因此，由于防止在第一码字部分序列中出现接收质量特性差的部分，结果是可以提高接收质量特性和系统吞吐量。

9. 发明申请

US20110173507A1 Interleaving/De-Interleaving Method, Soft-In/Soft-Out Decoding Method and Error Correction Code Encoder and Decoder Utilizing the Same 有权
标题翻译：交错/去交错方式，软/软解码解码方法和纠错码编码器和解码器
公开(公告)号：US20110173507A1
公开(公告)日：2011-07-14
申请号：US12955709
申请日：2010-11-29
申请人： Cheng-Chi Wong , Hsi-Chia Chang
发明人： Cheng-Chi Wong , Hsi-Chia Chang
IPC分类号： H03M13/27 , G06F11/00
CPC分类号： H03M13/2775 , H03M13/2739 , H03M13/2753 , H03M13/2771 , H03M13/2957 , H03M13/2978 , H03M13/3905 , H03M13/3972
摘要： An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.
摘要翻译：提供纠错码编码器。第一编码器对输入信息比特进行编码并产生第一奇偶校验位。交织器对输入信息比特进行交织并产生置换的信息比特。第二编码器对置换的信息位进行编码，并产生第二奇偶校验位。交织器以窗口方式对输入信息比特进行交织，使得输入信息比特在被交织之前被划分为输入信息比特窗口，此后产生具有置换信息比特的置换信息比特窗口。当输入信息比特窗口根据不同窗口索引特性被分组成组时，每个置换的信息比特窗口的窗口索引具有与其交错的对应的输入信息比特窗口的特征相同的特征。

10. 发明申请

US20110075615A1 RECURSIVE REALIZATION OF POLYNOMIAL PERMUTATION INTERLEAVING 有权
标题翻译：多元实时交互的实现
公开(公告)号：US20110075615A1
公开(公告)日：2011-03-31
申请号：US12571319
申请日：2009-09-30
申请人： Hanfang Pan , Michael A. Howard , Yongbin Wei , Michael A. Kongelf
发明人： Hanfang Pan , Michael A. Howard , Yongbin Wei , Michael A. Kongelf
IPC分类号： H04W4/00 , G06F1/16
CPC分类号： H03M13/2775 , H03M13/2739 , H03M13/2764 , H03M13/6502 , H03M13/6505 , H03M13/6525
摘要： Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.
摘要翻译：描述了在turbo解码期间便于自动生成交错地址的系统和方法。可以采用一种有效的递归技术，其中嵌套循环层能够计算多项式和从查询表给出交织参数“a”和“b”的模块化函数。使用递归技术，可以产生交织地址，每个时钟周期的一个交织地址可以保持turbo解码性能。

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