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1. 发明授权

US09441309B2 Electrode and method of forming the master electrode 有权
公开(公告)号：US09441309B2
公开(公告)日：2016-09-13
申请号：US14135745
申请日：2013-12-20
申请人： LUXEMBOURG INSTITUTE OF SCIENCE AND TECHNOLOGY (LIST)
发明人： Mikael Fredenberg , Patrik Möller , Peter Wiwen-Nilsson , Cecilia Aronsson , Matteo Dainese
IPC分类号： C25D1/00 , C25D1/10 , C25D5/02 , B81C99/00 , C25D5/10 , C25F3/14 , H01L21/288 , H01L21/3213 , H01L21/768 , H05K3/07 , H05K3/24 , H05K3/46 , C23C14/34 , C25D5/50 , C25D7/12 , H05K3/10
CPC分类号： C25D5/02 , B81C99/0085 , C23C14/34 , C23C14/3414 , C25D1/003 , C25D1/10 , C25D5/022 , C25D5/10 , C25D5/50 , C25D7/12 , C25D7/123 , C25F3/14 , H01L21/2885 , H01L21/32134 , H01L21/76838 , H01L21/76843 , H01L21/76852 , H01L21/76873 , H01L21/76877 , H01L21/76885 , H05K3/07 , H05K3/108 , H05K3/241 , H05K3/4647 , H05K2203/0117 , H05K2203/0733 , Y10T156/10
摘要： An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier provided with an insulating layer which is patterned at a front side. Conducting material in an electrode layer is applied in the cavities of the patterned insulating layer and in contact with the carrier. A connection layer is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.

2. 发明授权

US08114267B2 Method of monitoring a substrate patterning process 失效
标题翻译：监测基板图案化工艺的方法
公开(公告)号：US08114267B2
公开(公告)日：2012-02-14
申请号：US11976633
申请日：2007-10-26
申请人： Staffan Nordlinder , Nathaniel D. Robinson , Payman Therani
发明人： Staffan Nordlinder , Nathaniel D. Robinson , Payman Therani
IPC分类号： G02F1/00
CPC分类号： H05K1/0268 , H05K3/02 , H05K3/07 , H05K2201/0329 , H05K2203/0117 , H05K2203/0121 , H05K2203/0143 , H05K2203/105 , H05K2203/1142 , H05K2203/1545 , H05K2203/163
摘要： A method for monitoring a substrate patterning process, where at least two electrodes are used to apply a voltage to the substrate to cause a reaction in a portion of the substrate, that includes recording a current driven by said voltage as a function of time and/or as a function of a position of the substrate or a patterning mask. Also disclosed are a device and a computer program product for monitoring the substrate patterning process.
摘要翻译：一种用于监测衬底图案化工艺的方法，其中使用至少两个电极向衬底施加电压以在衬底的一部分中引起反应，包括记录由所述电压驱动的电流作为时间和/ 或者作为衬底或图案掩模的位置的函数。还公开了用于监测基板图案化工艺的装置和计算机程序产品。

3. 发明授权

US07998330B2 Direct nanoscale patterning of metals using polymer electrolytes 有权
标题翻译：使用聚合物电解质直接纳米级金属图案化
公开(公告)号：US07998330B2
公开(公告)日：2011-08-16
申请号：US12122967
申请日：2008-05-19
申请人： Nicholas X. Fang , Placid M. Ferreira , Keng Hao Hsu , Peter Lee Schultz , Kyle E. Jacobs , Anil Kumar
发明人： Nicholas X. Fang , Placid M. Ferreira , Keng Hao Hsu , Peter Lee Schultz , Kyle E. Jacobs , Anil Kumar
IPC分类号： C25D5/02 , C25D17/00
CPC分类号： B23H3/00 , B23H3/04 , B81C1/0046 , B81C2201/0154 , C25D1/00 , C25D1/006 , C25D5/02 , C25D11/22 , C25D17/007 , G01Q80/00 , H01L21/32134 , H05K3/07 , H05K2203/0108 , H05K2203/0117
摘要： Disclosed herein are electrochemical fabrication platforms for making structures, arrays of structures and functional devices having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods, systems and system components use an electrochemical stamping tool such as solid state polymeric electrolytes for generating patterns of relief and/or recessed features exhibiting excellent reproducibility, pattern fidelity and resolution on surfaces of solid state ionic conductors and in metal. Electrochemical stamping tools are capable high throughput patterning of large substrate areas, are compatible with commercially attractive manufacturing pathways to access a range of functional systems and devices including nano- and micro-electromechanical systems, sensors, energy storage devices, metal masks for printing, interconnects, and integrated electronic circuits.
摘要翻译：本文公开了用于制造具有选定的纳米尺寸和/或微尺寸物理尺寸，形状和空间取向的结构，结构阵列和功能装置的电化学制造平台。方法，系统和系统组件使用电化学冲压工具，例如固态聚合物电解质，用于产生在固态离子导体和金属表面上显示出优异的再现性，图案保真度和分辨率的浮雕和/或凹陷特征图案。电化学冲压工具能够对大衬底区域进行高通量图案化，与商业上有吸引力的制造途径兼容，以访问一系列功能系统和设备，包括纳米和微机电系统，传感器，能量存储设备，印刷用金属掩模，互连，和集成电子电路。

4. 发明授权

US07930815B2 Conductive pattern and method of making 有权
标题翻译：导电图案和制作方法
公开(公告)号：US07930815B2
公开(公告)日：2011-04-26
申请号：US11584690
申请日：2006-10-20
申请人： James P. Coleman , David N. Edwards , Ian J. Forster , Pradeep S. Iyer , Mark A. Licon
发明人： James P. Coleman , David N. Edwards , Ian J. Forster , Pradeep S. Iyer , Mark A. Licon
IPC分类号： H01P11/00 , G08B13/14
CPC分类号： G06K19/0776 , G06K19/07718 , G06K19/07749 , G06K19/07752 , G06K19/07779 , G06K19/07783 , H05K3/00 , H05K3/205 , H05K3/245 , H05K3/386 , H05K2203/0117 , Y10T29/49016 , Y10T29/49018 , Y10T29/4902 , Y10T29/49117 , Y10T29/49155 , Y10T29/49224
摘要： A method of forming an electrically-conductive pattern includes selectively electroplating the top portions of a substrate that corresponds to the pattern, and separating the conductive pattern from the substrate. The electroplating may also include electrically connecting the conductive pattern to an electrical component. Conductive ink, such as ink including carbon particles, may be selectively placed on the conductive substrate to facilitate plating of the desired pattern and/or to facilitate separation of the pattern from the substrate. An example of a conductive pattern is an antenna for a radio-frequency identification (RFID) device such as a label or a tag. One example of an electrical component that may be electrically connected to the antenna, is an RFID strap or chip.
摘要翻译：形成导电图案的方法包括选择性地电镀对应于图案的衬底的顶部部分，并且将导电图案与衬底分离。电镀还可以包括将导电图案电连接到电气部件。诸如包含碳颗粒的墨的导电油墨可以选择性地放置在导电基底上，以便于电镀所需图案和/或促进图案与基底的分离。导电图案的示例是用于诸如标签或标签的射频识别（RFID）设备的天线。可以电连接到天线的电气部件的一个例子是RFID带或芯片。

5. 发明授权

US07887688B2 Process for producing electronic circuit 失效
标题翻译：电子电路生产工艺
公开(公告)号：US07887688B2
公开(公告)日：2011-02-15
申请号：US11497045
申请日：2006-08-01
申请人： Isao Takasu
发明人： Isao Takasu
IPC分类号： C25D13/12 , C25D13/16
CPC分类号： C25D1/12 , C25D1/20 , C25D1/22 , G03G17/04 , H05K3/1266 , H05K3/207 , H05K2203/0117 , H05K2203/0517
摘要： Disclosed is a production process of an electronic circuit that can efficiently form a highly accurate electrically conductive pattern. The production process comprises the steps of: adhering insulating particles onto an electrically conductive base material to form an insulating pattern comprising a pattern region and a nonpattern region on the electrically conductive base material; adhering electrically conductive particles to the nonpattern region by first electrophoretic treatment; removing the pattern region by second electrophoretic treatment; and transferring the electrically conductive particles onto a recording medium to form an electrically conductive pattern of the electrically conductive particles onto the recording medium.
摘要翻译：公开了能够有效地形成高精度导电图案的电子电路的制造方法。该制造方法包括以下步骤：将绝缘颗粒粘附到导电基材上以形成在导电性基材上形成图案区域和非图案区域的绝缘图案; 通过第一次电泳处理将导电颗粒粘附到非图案区域; 通过第二次电泳处理去除图案区域; 并将导电颗粒转移到记录介质上，以将导电颗粒的导电图案形成到记录介质上。

6. 发明申请

US20090071837A1 MASTER ELECTRODE AND METHOD OF FORMING IT 审中-公开
标题翻译：主电极及其形成方法
公开(公告)号：US20090071837A1
公开(公告)日：2009-03-19
申请号：US12094142
申请日：2006-11-20
申请人： Mikael Fredenberg , Patrik Moller , Peter Wiwen-Nilsson , Cecilia Aronsson , Matteo Dainese
发明人： Mikael Fredenberg , Patrik Moller , Peter Wiwen-Nilsson , Cecilia Aronsson , Matteo Dainese
IPC分类号： C25D5/02 , C25D17/00 , C25D5/00 , C25F3/02 , C25C7/02
CPC分类号： C25D5/02 , B81C99/0085 , C23C14/34 , C23C14/3414 , C25D1/003 , C25D1/10 , C25D5/022 , C25D5/10 , C25D5/50 , C25D7/12 , C25D7/123 , C25F3/14 , H01L21/2885 , H01L21/32134 , H01L21/76838 , H01L21/76843 , H01L21/76852 , H01L21/76873 , H01L21/76877 , H01L21/76885 , H05K3/07 , H05K3/108 , H05K3/241 , H05K3/4647 , H05K2203/0117 , H05K2203/0733 , Y10T156/10
摘要： A system and method comprising a master electrode arranged on substrate, said master electrode comprising a pattern layer, least partly of an insulating material and having a first surface provided with a plurality of cavities in which a conducting material is arranged, said electrode conducting material being electrically connected to at least one electrode current supply contact; said substrate comprising a top surface in contact with or arranged adjacent said first surface and having conducting material and/or structures of a conducting material arranged thereon, said substrate conducting material being electrically connected to at least one current supply contact; whereby a plurality of electrochemical cells are formed delimited by said cavities, said substrate conducting material and said electrode conducting material, said cells comprising an electrolyte; herein an electrode resistance between said electrode conducting material and said electrode current supply contact and a substrate resistance between said substrate conducting material and said substrate current supply contact are adapted for providing a predetermined current density in each electrochemical cell.
摘要翻译：一种包括布置在基板上的主电极的系统和方法，所述主电极包括至少部分绝缘材料的图案层，并且具有设置有多个空腔的第一表面，其中布置有导电材料，所述电极导电材料为电连接到至少一个电极电流供应触点; 所述衬底包括与所述第一表面接触或布置的顶表面，并且具有布置在其上的导电材料的导电材料和/或结构，所述衬底导电材料电连接到至少一个电流供应触点; 由此由多个电化学电池形成，由所述空腔，所述衬底导电材料和所述电极导电材料界定，所述电池包括电解质; 这里，所述电极导电材料和所述电极电流供应触点之间的电极电阻和所述衬底导电材料与所述衬底电流供应触点之间的衬底电阻适于在每个电化学电池中提供预定的电流密度。

7. 发明申请

US20080079890A1 Pattern forming apparatus and pattern forming method 有权
标题翻译：图案形成装置和图案形成方法
公开(公告)号：US20080079890A1
公开(公告)日：2008-04-03
申请号：US11904923
申请日：2007-09-27
申请人： Hiroto Sugahara
发明人： Hiroto Sugahara
IPC分类号： G02F1/1345
CPC分类号： H05K3/207 , H05K3/125 , H05K3/1266 , H05K2203/0117 , H05K2203/013 , H05K2203/0517 , Y10S101/37
摘要： A pattern forming apparatus which forms a pattern of an electroconductive liquid on a printing medium includes a pattern forming substrate having an insulating substrate, a plurality of electrodes arranged on the insulating substrate, and an insulating layer which covers the electrodes, an electric potential controller which selectively applies an electric potential to the electrodes, and a transferring mechanism which transfers the pattern by bringing the electroconductive liquid formed as a predetermined pattern on the insulating layer, in contact with the printing medium. Accordingly, it is possible to form a fine pattern at a low cost.
摘要翻译：在打印介质上形成导电液体图案的图形形成装置包括具有绝缘基板的图案形成基板，布置在绝缘基板上的多个电极和覆盖电极的绝缘层，电位控制器选择性地向电极施加电位，以及通过使形成为预定图案的导电液体与印刷介质接触而在绝缘层上传送图案的转印机构。因此，可以以低成本形成精细图案。

8. 发明申请

US20070151858A1 Method and electrode for defining and replicating structures in conducting materials 审中-公开
标题翻译：用于定义和复制导电材料结构的方法和电极
公开(公告)号：US20070151858A1
公开(公告)日：2007-07-05
申请号：US11716166
申请日：2007-03-09
申请人： Patrik Moller , Mikael Fredenberg , Peter Wivon-Nilsson
发明人： Patrik Moller , Mikael Fredenberg , Peter Wivon-Nilsson
IPC分类号： C25D5/02
CPC分类号： H05K3/205 , C25D5/02 , C25D7/12 , C25F3/14 , H05K3/00 , H05K3/07 , H05K2203/0117
摘要： The present invention concerns an electrochemical pattern replication method, ECPR, and a construction of a conductive electrode for production of applications involving micro and nano structures. An etching or plating pattern, which is defined by a conductive electrode, a master electrode, is replicated on an electrically conductive material, a substrate. The master electrode is put in close contact with the substrate and the etching/plating pattern is directly transferred onto the substrate by using a contact etching/plating process. The contact etching/plating process is performed in local etching/plating cells, that are formed in closed or open cavities between the master electrode and the substrate.
摘要翻译：本发明涉及一种电化学图案复制方法，ECPR，以及用于生产涉及微结构和纳米结构的应用的导电电极的结构。由导电电极，主电极限定的蚀刻或电镀图案被复制在导电材料，基板上。主电极与衬底紧密接触，并且通过使用接触蚀刻/电镀工艺将蚀刻/电镀图案直接转印到衬底上。接触蚀刻/电镀工艺在局部蚀刻/电镀电池中进行，其形成在主电极和基板之间的闭合或敞开的空腔中。

9. 发明授权

US5197184A Method of forming three-dimensional circuitry 失效
标题翻译：形成三维电路的方法
公开(公告)号：US5197184A
公开(公告)日：1993-03-30
申请号：US580758
申请日：1990-09-11
申请人： William R. Crumly , Christopher M. Schreiber , Haim Feigenbaum
发明人： William R. Crumly , Christopher M. Schreiber , Haim Feigenbaum
IPC分类号： H05K1/11 , H05K3/20 , H05K3/40 , H05K3/46
CPC分类号： H05K3/205 , H05K3/4007 , H05K3/4647 , H05K3/4682 , H05K2201/0367 , H05K2201/0394 , H05K2201/09509 , H05K2203/0108 , H05K2203/0113 , H05K2203/0117 , H05K2203/0726 , Y10T29/49155 , Y10T29/49158
摘要： A pressure-type contact for flexible or conventional wire cable terminations is fabricated from electroformed thin metallic wafers (100) in which one wafer is plated with a raised conductive interconnection feature (122). The electrical circuitry (118, 120) is made on a stainless steel mandrel (10, 10a) having a TEFLON pattern (16, 16a) on its surface that allows the desired electrical circuit (30, 32, 34, 30a, 32a, 34a, 78) to be electrolytically plated upon the conductive mandrel surface. The mandrel surface is formed with projecting features in the form of depressions (24, 24a) that will form a series of dots or raised interconnection features on the termination wafers. The mandrel also has projecting posts (76) for providing electrical connection through the substrate.

10. 发明授权

US5055637A Circuit boards with recessed traces 失效
标题翻译：具有凹痕的电路板
公开(公告)号：US5055637A
公开(公告)日：1991-10-08
申请号：US434427
申请日：1989-11-13
申请人： George R. Hagner
发明人： George R. Hagner
IPC分类号： H05K1/11 , H05K1/18 , H05K3/00 , H05K3/08 , H05K3/10 , H05K3/18 , H05K3/20 , H05K3/24 , H05K3/34 , H05K3/42
CPC分类号： H05K3/20 , H05K1/111 , H05K1/183 , H05K3/08 , H05K3/107 , H05K3/3473 , H05K2201/0129 , H05K2201/0376 , H05K2201/09036 , H05K2201/09118 , H05K2201/09472 , H05K2201/0959 , H05K2201/09845 , H05K2201/09981 , H05K2201/10636 , H05K2201/10681 , H05K2203/0117 , H05K2203/0278 , H05K2203/042 , H05K2203/0726 , H05K2203/0769 , H05K3/0094 , H05K3/108 , H05K3/184 , H05K3/244 , H05K3/3421 , H05K3/3442 , H05K3/3452 , H05K3/42 , H05K3/426 , Y02P70/611
摘要： Circuit boards with imbedded traces, which may form grooves or trenches are provided. The traces may be at least partially filled with a reflowable conductive material such as solder. The grooves may be selectively furnished with solder while other regions may be empty or void of solder. In assembling electronic components, with or without extended leads, such as surface mount integrated circuits or chips, to the solder core circuit boards, the leads may be placed within the regions of the grooves without solder (contact regions) and then the circuit board may be heated selectively or as a whole to reflow the solder to the bonding or contacting regions to bond the traces to the leads upon cooling. Circuit boards having surface mount devices on both sides may be formed in this manner. Further, tape automated bonded or TAB mounted devices may be directly placed into and bonded to the traces or solder core circuit boards with minimum exposure of the excised TAB leads prior to assembly. In one form, the grooves are plated with copper before they are filled with solder. Alternatively, the solder may be present only in cavities or pockets next to the contact regions where the component lead will connect with the conductive material pattern.
摘要翻译：提供具有嵌入痕迹的电路板，其可以形成凹槽或沟槽。迹线可以至少部分地填充有可回流的导电材料，例如焊料。凹槽可以选择性地装备有焊料，而其它区域可能是空的或者没有焊料。在组装电子部件的情况下，将带有或不具有延伸引线（例如表面贴装集成电路或芯片）的电子部件组装到焊料芯电路板上，可以将引线放置在槽的区域内而不用焊料（接触区域），然后电路板可以被选择性地或作为整体加热以将焊料回流到接合或接触区域，以在冷却时将迹线结合到引线。可以以这种方式形成具有两侧表面安装装置的电路板。此外，胶带自动粘合或TAB安装的装置可以在组装之前以最小的切割的TAB导线的暴露直接放置到轨迹或焊芯电路板中并结合到轨迹或焊芯电路板。在一种形式中，在填充有焊料之前，将槽镀铜。或者，焊料可以仅存在于部件引线将与导电材料图案连接的接触区域旁边的腔或袋中。

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