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1. 发明申请

US20110158376A1 SHIFT REGISTER 有权
公开(公告)号：US20110158376A1
公开(公告)日：2011-06-30
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/34
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

2. 发明授权

US11151916B2 Data shifting circuit for a current mode display 有权
公开(公告)号：US11151916B2
公开(公告)日：2021-10-19
申请号：US16761767
申请日：2018-11-01
申请人： Facebook Technologies, LLC
发明人： William Thomas Blank , Ilias Pappas
IPC分类号： G09G3/02 , G11C19/28 , G11C19/18 , G11C13/04 , G11C19/34 , G11C19/30
摘要： Techniques are described for operating a display comprising an array of emitters arranged in at least one column. A data shifting circuit stores digital data or an analog representation thereof in a first storage element. The data shifting circuit outputs the digital data or analog representation multiple times to a display driver circuit, using a multiplexer. The first storage element can be a shift register or a capacitor. Digital data can be internally shifted within the data shifting circuit, through multiple shift registers, prior to output to the display driver circuit. An analog representation can be stored and read from the same capacitor without internal shifting. The display driver circuit drives a different emitter of the column each time. A scanning assembly including a reflective surface that receives light from the emitter array forms an output image by rotating the reflective surface in synchronization with driving of the emitters.

3. 发明授权

US09424893B2 Systems and methods for acoustic wave enabled data storage 有权
公开(公告)号：US09424893B2
公开(公告)日：2016-08-23
申请号：US14308593
申请日：2014-06-18
申请人： Elwha LLC
发明人： Philip Lionel Barnes , Hon Wah Chin , Howard Lee Davidson , Kimberly D. A. Hallman , Roderick A. Hyde , Muriel Y. Ishikawa , Jordin T. Kare , Brian Lee , Richard T. Lord , Robert W. Lord , Craig J. Mundie , Nathan P. Myhrvold , Nicholas F. Pasch , Eric D. Rudder , Clarence T. Tegreene , Marc Tremblay , David B. Tuckerman , Charles Whitmer , Lowell L. Wood, Jr.
IPC分类号： G11C7/10 , G10K11/00 , G11C5/02 , G11C7/00 , G11C11/56 , G11C19/00 , G11C19/08 , G11C19/28 , G11C19/34 , G10K15/00
CPC分类号： G11C7/10 , G10K11/00 , G10K15/00 , G11C5/02 , G11C7/005 , G11C11/56 , G11C19/00 , G11C19/08 , G11C19/28 , G11C19/34
摘要： The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift registers may physically shift particles along rows and/or columns of wells through the interactions of two parallel surfaces. A transducer may generate an acoustic wave to displace one or more of the two parallel surfaces. The particles may be transferred to and/or otherwise constrained by a buffer surface during at least a portion of the acoustic wave, such that the particles may be shifted during one or more cycles of the acoustic wave. In various embodiments, the amplitude of the acoustic wave may correspond to the spacing distance between each of the wells. The wells may be physical and/or potential wells.

4. 发明授权

US10937348B2 Analog data shifter for a current mode display 有权
公开(公告)号：US10937348B2
公开(公告)日：2021-03-02
申请号：US16178505
申请日：2018-11-01
申请人： Facebook Technologies, LLC
发明人： William Thomas Blank , Ilias Pappas
IPC分类号： G09G3/02 , G11C19/28 , G11C19/18 , G11C13/04 , G11C19/34 , G11C19/30
摘要： Techniques are described for operating a display comprising an array of emitters arranged in at least one column. Data is shifted through the emitters of the column using a data shifting circuit. The data can be shifted sequentially, one emitter at a time. The data shifting circuit includes storage elements for temporary storage of the data as it is shifted down the column. The data can be stored as a charge on a capacitor, where the capacitor is charged to a particular voltage according to a current from a current mirror. The shifting can be performed in synchronization with scanning of the emitters by a scanning assembly, where the scanning produces an output image for viewing by a user.

5. 发明申请

US20200372846A1 DATA SHIFTING CIRCUIT FOR A CURRENT MODE DISPLAY 审中-公开
公开(公告)号：US20200372846A1
公开(公告)日：2020-11-26
申请号：US16761767
申请日：2018-11-01
申请人： Facebook Technologies, LLC
发明人： William Thomas BLANK , Ilias PAPPAS
IPC分类号： G09G3/02 , G11C13/04 , G11C19/18 , G11C19/28 , G11C19/30 , G11C19/34
摘要： Techniques are described for operating a display comprising an array of emitters arranged in at least one column. A data shifting circuit stores digital data or an analog representation thereof in a first storage element. The data shifting circuit outputs the digital data or analog representation multiple times to a display driver circuit, using a multiplexer. The first storage element can be a shift register or a capacitor. Digital data can be internally shifted within the data shifting circuit, through multiple shift registers, prior to output to the display driver circuit. An analog representation can be stored and read from the same capacitor without internal shifting. The display driver circuit drives a different emitter of the column each time. A scanning assembly including a reflective surface that receives light from the emitter array forms an output image by rotating the reflective surface in synchronization with driving of the emitters.

6. 发明申请

US20160099717A1 TRANSMISSION CIRCUIT, INTEGRATED CIRCUIT, AND PARALLEL-TO-SERIAL CONVERSION METHOD 有权
标题翻译：传输电路，集成电路和并行转换方法
公开(公告)号：US20160099717A1
公开(公告)日：2016-04-07
申请号：US14854961
申请日：2015-09-15
申请人： SOCIONEXT INC.
发明人： Masanori YOSHITANI
IPC分类号： H03L7/00 , G11C19/34 , H03M9/00
CPC分类号： H03L7/00 , G11C19/00 , G11C19/28 , G11C19/34 , H03M9/00
摘要： A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal.
摘要翻译：发送电路包括：移位寄存器，被配置为与多个触发器电路中的第一时钟信号同步地输入并行数据; 控制电路，被配置为根据所述第一时钟信号的相位输出相位的第二时钟信号; 选择器，被配置为选择多个触发器电路的输入并行数据和输出并行数据中的任何一个; 以及转换电路，被配置为将所述选择器选择的并行数据与所述第二时钟信号同步地转换为多个串行数据，其中所述控制电路根据所述控制电路的选择信号向所述选择器输出选择信号检测到第一时钟信号的相位。

7. 发明授权

US09654114B2 Transmission circuit, integrated circuit, and parallel-to-serial conversion method 有权
公开(公告)号：US09654114B2
公开(公告)日：2017-05-16
申请号：US14854961
申请日：2015-09-15
申请人： SOCIONEXT INC.
发明人： Masanori Yoshitani
IPC分类号： H03L7/00 , H03M9/00 , G11C19/34 , G11C19/00 , G11C19/28
CPC分类号： H03L7/00 , G11C19/00 , G11C19/28 , G11C19/34 , H03M9/00
摘要： A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal.

8. 发明申请

US20150295560A1 RESET SCHEME FOR SCAN CHAINS WITH ASYNCHRONOUS RESET SIGNALS 有权
标题翻译：具有异步复位信号的扫描链复位方案
公开(公告)号：US20150295560A1
公开(公告)日：2015-10-15
申请号：US14251297
申请日：2014-04-11
申请人： QUALCOMM Incorporated
发明人： Dipti Ranjan PAL , Paul Ivan PENZES , Wai Kit SIU
IPC分类号： H03K3/012 , G11C19/34 , H03K3/037
CPC分类号： H03K3/012 , G01R31/318536 , G01R31/318541 , G01R31/318594 , G11C19/34 , H03K3/0375
摘要： A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.
摘要翻译：第一装置包括至少一个扫描链。所述至少一个扫描链中的每一个包括耦合在一起的扫描单元。当扫描单元的复位状态是第一状态时，至少一个扫描链中的每个扫描单元包括第一类型的扫描单元，当扫描单元的复位状态是第二状态时，包括第二类型的扫描单元。所述至少一个扫描链的一个或多个扫描链包括所述第一类型的扫描单元和所述第二类型的扫描单元中的至少一个。第二装置包括第一和第二组扫描链，包括没有设置和复位功能的触发器。第一组扫描链和第二组扫描链中的每个触发器分别具有第一状态和第二状态的复位状态。

9. 发明申请

US20050017065A1 Bidirectional shift register and display device incorporating same 失效
标题翻译：双向移位寄存器和包含其的显示装置
公开(公告)号：US20050017065A1
公开(公告)日：2005-01-27
申请号：US10860660
申请日：2004-06-04
申请人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
发明人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
IPC分类号： G11C19/00 , G06F5/01 , G06F17/00 , G09F9/00 , G09G3/00 , G09G3/20 , G09G3/36 , G11C8/04 , G11C19/28 , G11C19/34 , H03K23/44
CPC分类号： G06F5/01 , G09G3/006 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0289 , G09G2330/12
摘要： The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.
摘要翻译：本发明包括：移位寄存器部分，包括与时钟信号同步操作的多级触发器，用于根据外部提供的方向指示信号切换移位方向; 波形变化部分，用于改变处于第一预定阶段的触发器之一的信号输出的波形; 以及检查信号切换部，根据方向指示信号，切换波形变化部中波形变化的信号输出与第二个触发器中的一个触发器的信号输出之间的输出预定阶段。

10. 发明授权

US10930188B2 Feedback circuit for calibrating a current mode display 有权
公开(公告)号：US10930188B2
公开(公告)日：2021-02-23
申请号：US16178510
申请日：2018-11-01
申请人： Facebook Technologies, LLC
发明人： William Thomas Blank , Ilias Pappas
IPC分类号： G09G3/02 , G11C19/28 , G11C19/18 , G11C13/04 , G11C19/34 , G11C19/30
摘要： Techniques are described for collecting feedback on a display comprising a plurality of emitters arranged in a column. Each emitter is driven by a respective emitter cell that generates a driving current for the emitter based on digital data or an analog representation thereof. The digital data or analog representation is sequentially shifted through the entire column. An electrical signal associated with a last emitter to be driven based on the digital data or analog representation is measured, along a feedback path formed by selectively opening or closing a first switch and a second switch, which are respectively connectable to an anode and a cathode of the last emitter. Since each emitter cell contributes to the electrical signal, the value of the electrical signal is indicative of whether there is a problem with an emitter cell somewhere in the column. The subsequently driving of the emitters is adjusted accordingly.

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